Low overhead design for programmable logic array with testability

K. C. Wei, J. J. Sheu, B. D. Liu

Research output: Contribution to journalArticle

Abstract

A new design to reduce the overhead required for a fully testable PLA is proposed. This design rearranges and groups the product lines into partitions. Then, one extra output line per partition is added to make the whole PLA testable. The silicon area overhead required by this design is significantly less than those of previous methods.

Original languageEnglish
Pages (from-to)241-250
Number of pages10
JournalInternational Journal of Electronics
Volume77
Issue number2
DOIs
Publication statusPublished - 1994 Aug

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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