Low-Leakage and low-power implementation of high-speed logic gates

Tsung-Yi Wu, Liang Ying Lu

Research output: Contribution to journalArticle

Abstract

In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates in this paper can improve leakage currents, dynamic power consumption, and propagation delays by averages of 42.4%, 8.1%, and 13.5%, respectively. Logic synthesizers can use them to facilitate power reduction. The experimental results show that a commercial power optimization tool can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by the tool contains our proposed gates.

Original languageEnglish
Pages (from-to)401-408
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE92-C
Issue number4
DOIs
Publication statusPublished - 2009 Jan 1

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Logic gates
Leakage currents
Transistors
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

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Low-Leakage and low-power implementation of high-speed logic gates. / Wu, Tsung-Yi; Lu, Liang Ying.

In: IEICE Transactions on Electronics, Vol. E92-C, No. 4, 01.01.2009, p. 401-408.

Research output: Contribution to journalArticle

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