Abstract
In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates in this paper can improve leakage currents, dynamic power consumption, and propagation delays by averages of 42.4%, 8.1%, and 13.5%, respectively. Logic synthesizers can use them to facilitate power reduction. The experimental results show that a commercial power optimization tool can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by the tool contains our proposed gates.
| Original language | English |
|---|---|
| Pages (from-to) | 401-408 |
| Number of pages | 8 |
| Journal | IEICE Transactions on Electronics |
| Volume | E92-C |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2009 Jan 1 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
}
Low-Leakage and low-power implementation of high-speed logic gates. / Wu, Tsung-Yi; Lu, Liang Ying.
In: IEICE Transactions on Electronics, Vol. E92-C, No. 4, 01.01.2009, p. 401-408.Research output: Contribution to journal › Article
TY - JOUR
T1 - Low-Leakage and low-power implementation of high-speed logic gates
AU - Wu, Tsung-Yi
AU - Lu, Liang Ying
PY - 2009/1/1
Y1 - 2009/1/1
N2 - In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates in this paper can improve leakage currents, dynamic power consumption, and propagation delays by averages of 42.4%, 8.1%, and 13.5%, respectively. Logic synthesizers can use them to facilitate power reduction. The experimental results show that a commercial power optimization tool can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by the tool contains our proposed gates.
AB - In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates in this paper can improve leakage currents, dynamic power consumption, and propagation delays by averages of 42.4%, 8.1%, and 13.5%, respectively. Logic synthesizers can use them to facilitate power reduction. The experimental results show that a commercial power optimization tool can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by the tool contains our proposed gates.
UR - http://www.scopus.com/inward/record.url?scp=77950425077&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77950425077&partnerID=8YFLogxK
U2 - 10.1587/transele.E92.C.401
DO - 10.1587/transele.E92.C.401
M3 - Article
AN - SCOPUS:77950425077
VL - E92-C
SP - 401
EP - 408
JO - IEICE Transactions on Electronics
JF - IEICE Transactions on Electronics
SN - 0916-8524
IS - 4
ER -