Abstract
In this paper, we propose novel transmissiongate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents, less dynamic power consumption, and shorter delays than conventional CMOS gates. Compared with the conventional 65nm CMOS gates, our proposed 65nm gates can improve leakage currents, dynamic power consumption, and propagation delays by averages of 29.5%, 15.3%, and 30.3%, respectively. Logic synthesizers can use our proposed gates to facilitate power reduction. The experimental results show that Power Compiler can further reduce the leakage current and dynamic power up to 35.0% and 20.0%, respectively, when the standard cell library used by Power Compiler contains our proposed gates.
| Original language | English |
|---|---|
| Title of host publication | 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC |
| DOIs | |
| Publication status | Published - 2008 Dec 1 |
| Event | 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC - Hong Kong, China Duration: 2008 Dec 8 → 2008 Dec 10 |
Publication series
| Name | 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC |
|---|
Other
| Other | 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC |
|---|---|
| Country | China |
| City | Hong Kong |
| Period | 08-12-08 → 08-12-10 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
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Low-leakage and low-power implementation of high-speed 65nm logic gates. / Wu, Tsung Yi; Lu, Liang Ying; Liang, Cheng Hsun.
2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC. 2008. 4760641 (2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Low-leakage and low-power implementation of high-speed 65nm logic gates
AU - Wu, Tsung Yi
AU - Lu, Liang Ying
AU - Liang, Cheng Hsun
PY - 2008/12/1
Y1 - 2008/12/1
N2 - In this paper, we propose novel transmissiongate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents, less dynamic power consumption, and shorter delays than conventional CMOS gates. Compared with the conventional 65nm CMOS gates, our proposed 65nm gates can improve leakage currents, dynamic power consumption, and propagation delays by averages of 29.5%, 15.3%, and 30.3%, respectively. Logic synthesizers can use our proposed gates to facilitate power reduction. The experimental results show that Power Compiler can further reduce the leakage current and dynamic power up to 35.0% and 20.0%, respectively, when the standard cell library used by Power Compiler contains our proposed gates.
AB - In this paper, we propose novel transmissiongate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents, less dynamic power consumption, and shorter delays than conventional CMOS gates. Compared with the conventional 65nm CMOS gates, our proposed 65nm gates can improve leakage currents, dynamic power consumption, and propagation delays by averages of 29.5%, 15.3%, and 30.3%, respectively. Logic synthesizers can use our proposed gates to facilitate power reduction. The experimental results show that Power Compiler can further reduce the leakage current and dynamic power up to 35.0% and 20.0%, respectively, when the standard cell library used by Power Compiler contains our proposed gates.
UR - http://www.scopus.com/inward/record.url?scp=63249126113&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=63249126113&partnerID=8YFLogxK
U2 - 10.1109/EDSSC.2008.4760641
DO - 10.1109/EDSSC.2008.4760641
M3 - Conference contribution
AN - SCOPUS:63249126113
SN - 9781424425402
T3 - 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC
BT - 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC
ER -