LAKE: a performance-driven analog CMOS cell layout generator

Zhi-Ming Lin, Yu Jung Huang, Kuo Hong Hsiau

Research output: Contribution to conferencePaperpeer-review


LAKE is an automatic layout generator that lays out CMOS analog integrated circuits subject to circuit layout constraints such as: matching, symmetry, signal coupling, cell aspect ratio (or cell height), and specified cell input/output pin locations. Unlike most previous works, LAKE focuses on effective rules and methods that suit any type of CMOS analog circuits to be fit in an application specific mixed analog digital layout system. Placement bases on the characteristics of circuit structure and the layout constraints. Proposed slot structure provides the capability in handling fully symmetry layouts. The simulated evolution process evaluates the quality of layout based on detailed layout information in pursuing minimal parasitic effects on circuit performance. We test some real life examples. The design experiments have shown that LAKE can produce manual-quality analog layouts.

Original languageEnglish
Number of pages6
Publication statusPublished - 1994 Dec 1
EventProceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems - Taipei, Taiwan
Duration: 1994 Dec 51994 Dec 8


OtherProceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems
CityTaipei, Taiwan

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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