Investigating the FIFO design styles based on the Balsa synthesis system

Ren-Der Chen; Che An Lee; Pei Hua Hsieh

doi:10.1109/ISICir.2011.6131906

Investigating the FIFO design styles based on the Balsa synthesis system

Ren-Der Chen, Che An Lee, Pei Hua Hsieh

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this paper, three asynchronous FIFO design styles, linear, square, and cubic, are investigated based on the Balsa synthesis system. These styles are designed with the key difference being the path by which data travels through the FIFO. The design with shorter path should result in lower latency and higher throughput, but will require more complicated control. All the FIFOs are designed using the Balsa language, and the area cost and simulation time are compared for each FIFO with varying sizes. A tool is also presented for automatic generation of Balsa code for each FIFO.

Original language	English
Title of host publication	2011 International Symposium on Integrated Circuits, ISIC 2011
Pages	176-179
Number of pages	4
DOIs	https://doi.org/10.1109/ISICir.2011.6131906
Publication status	Published - 2011 Dec 1
Event	2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore, Singapore Duration: 2011 Dec 12 → 2011 Dec 14

Publication series

Name	2011 International Symposium on Integrated Circuits, ISIC 2011

Other

Other	2011 International Symposium on Integrated Circuits, ISIC 2011
Country	Singapore
City	SingaporeSingapore
Period	11-12-12 → 11-12-14

Fingerprint

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

Chen, R-D., Lee, C. A., & Hsieh, P. H. (2011). Investigating the FIFO design styles based on the Balsa synthesis system. In 2011 International Symposium on Integrated Circuits, ISIC 2011 (pp. 176-179). [6131906] (2011 International Symposium on Integrated Circuits, ISIC 2011). https://doi.org/10.1109/ISICir.2011.6131906

@inproceedings{96fc0aa166114d2e96432d3c8bfc6491,

title = "Investigating the FIFO design styles based on the Balsa synthesis system",

abstract = "In this paper, three asynchronous FIFO design styles, linear, square, and cubic, are investigated based on the Balsa synthesis system. These styles are designed with the key difference being the path by which data travels through the FIFO. The design with shorter path should result in lower latency and higher throughput, but will require more complicated control. All the FIFOs are designed using the Balsa language, and the area cost and simulation time are compared for each FIFO with varying sizes. A tool is also presented for automatic generation of Balsa code for each FIFO.",

author = "Ren-Der Chen and Lee, {Che An} and Hsieh, {Pei Hua}",

year = "2011",

month = dec

day = "1",

doi = "10.1109/ISICir.2011.6131906",

language = "English",

isbn = "9781612848648",

series = "2011 International Symposium on Integrated Circuits, ISIC 2011",

pages = "176--179",

booktitle = "2011 International Symposium on Integrated Circuits, ISIC 2011",

note = "2011 International Symposium on Integrated Circuits, ISIC 2011 ; Conference date: 12-12-2011 Through 14-12-2011",

}

Chen, R-D, Lee, CA & Hsieh, PH 2011, Investigating the FIFO design styles based on the Balsa synthesis system. in 2011 International Symposium on Integrated Circuits, ISIC 2011., 6131906, 2011 International Symposium on Integrated Circuits, ISIC 2011, pp. 176-179, 2011 International Symposium on Integrated Circuits, ISIC 2011, SingaporeSingapore, Singapore, 11-12-12. https://doi.org/10.1109/ISICir.2011.6131906

TY - GEN

T1 - Investigating the FIFO design styles based on the Balsa synthesis system

AU - Chen, Ren-Der

AU - Lee, Che An

AU - Hsieh, Pei Hua

PY - 2011/12/1

Y1 - 2011/12/1

N2 - In this paper, three asynchronous FIFO design styles, linear, square, and cubic, are investigated based on the Balsa synthesis system. These styles are designed with the key difference being the path by which data travels through the FIFO. The design with shorter path should result in lower latency and higher throughput, but will require more complicated control. All the FIFOs are designed using the Balsa language, and the area cost and simulation time are compared for each FIFO with varying sizes. A tool is also presented for automatic generation of Balsa code for each FIFO.

AB - In this paper, three asynchronous FIFO design styles, linear, square, and cubic, are investigated based on the Balsa synthesis system. These styles are designed with the key difference being the path by which data travels through the FIFO. The design with shorter path should result in lower latency and higher throughput, but will require more complicated control. All the FIFOs are designed using the Balsa language, and the area cost and simulation time are compared for each FIFO with varying sizes. A tool is also presented for automatic generation of Balsa code for each FIFO.

UR - http://www.scopus.com/inward/record.url?scp=84863016577&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84863016577&partnerID=8YFLogxK

U2 - 10.1109/ISICir.2011.6131906

DO - 10.1109/ISICir.2011.6131906

M3 - Conference contribution

AN - SCOPUS:84863016577

SN - 9781612848648

T3 - 2011 International Symposium on Integrated Circuits, ISIC 2011

SP - 176

EP - 179

BT - 2011 International Symposium on Integrated Circuits, ISIC 2011

T2 - 2011 International Symposium on Integrated Circuits, ISIC 2011

Y2 - 12 December 2011 through 14 December 2011

ER -

Access to Document

10.1109/ISICir.2011.6131906