Investigating the FIFO design styles based on the Balsa synthesis system

Ren-Der Chen, Che An Lee, Pei Hua Hsieh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, three asynchronous FIFO design styles, linear, square, and cubic, are investigated based on the Balsa synthesis system. These styles are designed with the key difference being the path by which data travels through the FIFO. The design with shorter path should result in lower latency and higher throughput, but will require more complicated control. All the FIFOs are designed using the Balsa language, and the area cost and simulation time are compared for each FIFO with varying sizes. A tool is also presented for automatic generation of Balsa code for each FIFO.

Original languageEnglish
Title of host publication2011 International Symposium on Integrated Circuits, ISIC 2011
Pages176-179
Number of pages4
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore, Singapore
Duration: 2011 Dec 122011 Dec 14

Publication series

Name2011 International Symposium on Integrated Circuits, ISIC 2011

Other

Other2011 International Symposium on Integrated Circuits, ISIC 2011
CountrySingapore
CitySingaporeSingapore
Period11-12-1211-12-14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Chen, R-D., Lee, C. A., & Hsieh, P. H. (2011). Investigating the FIFO design styles based on the Balsa synthesis system. In 2011 International Symposium on Integrated Circuits, ISIC 2011 (pp. 176-179). [6131906] (2011 International Symposium on Integrated Circuits, ISIC 2011). https://doi.org/10.1109/ISICir.2011.6131906