Abstract
In this paper, three asynchronous FIFO design styles, linear, square, and cubic, are investigated based on the Balsa synthesis system. These styles are designed with the key difference being the path by which data travels through the FIFO. The design with shorter path should result in lower latency and higher throughput, but will require more complicated control. All the FIFOs are designed using the Balsa language, and the area cost and simulation time are compared for each FIFO with varying sizes. A tool is also presented for automatic generation of Balsa code for each FIFO.
| Original language | English |
|---|---|
| Title of host publication | 2011 International Symposium on Integrated Circuits, ISIC 2011 |
| Pages | 176-179 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2011 Dec 1 |
| Event | 2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore, Singapore Duration: 2011 Dec 12 → 2011 Dec 14 |
Publication series
| Name | 2011 International Symposium on Integrated Circuits, ISIC 2011 |
|---|
Other
| Other | 2011 International Symposium on Integrated Circuits, ISIC 2011 |
|---|---|
| Country | Singapore |
| City | SingaporeSingapore |
| Period | 11-12-12 → 11-12-14 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
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Investigating the FIFO design styles based on the Balsa synthesis system. / Chen, Ren-Der; Lee, Che An; Hsieh, Pei Hua.
2011 International Symposium on Integrated Circuits, ISIC 2011. 2011. p. 176-179 6131906 (2011 International Symposium on Integrated Circuits, ISIC 2011).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Investigating the FIFO design styles based on the Balsa synthesis system
AU - Chen, Ren-Der
AU - Lee, Che An
AU - Hsieh, Pei Hua
PY - 2011/12/1
Y1 - 2011/12/1
N2 - In this paper, three asynchronous FIFO design styles, linear, square, and cubic, are investigated based on the Balsa synthesis system. These styles are designed with the key difference being the path by which data travels through the FIFO. The design with shorter path should result in lower latency and higher throughput, but will require more complicated control. All the FIFOs are designed using the Balsa language, and the area cost and simulation time are compared for each FIFO with varying sizes. A tool is also presented for automatic generation of Balsa code for each FIFO.
AB - In this paper, three asynchronous FIFO design styles, linear, square, and cubic, are investigated based on the Balsa synthesis system. These styles are designed with the key difference being the path by which data travels through the FIFO. The design with shorter path should result in lower latency and higher throughput, but will require more complicated control. All the FIFOs are designed using the Balsa language, and the area cost and simulation time are compared for each FIFO with varying sizes. A tool is also presented for automatic generation of Balsa code for each FIFO.
UR - http://www.scopus.com/inward/record.url?scp=84863016577&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84863016577&partnerID=8YFLogxK
U2 - 10.1109/ISICir.2011.6131906
DO - 10.1109/ISICir.2011.6131906
M3 - Conference contribution
AN - SCOPUS:84863016577
SN - 9781612848648
T3 - 2011 International Symposium on Integrated Circuits, ISIC 2011
SP - 176
EP - 179
BT - 2011 International Symposium on Integrated Circuits, ISIC 2011
ER -