In this paper, an integrated synthesis system is established to synthesize speed-independent asynchronous circuits directly from STGs with limited fanin basic gates. It combines asynchronous technology mapping and synthesis into an integrated one and thus can get the mapping solution for those whose mapping results can not be generated by previous separate mapping methods. In addition, the whole synthesis is carried out entirely on the STG level without generating the SGs and thereby preserve the problem size proportional to the number of signals. With the proposed method, STGs can be synthesized and hazard-free mapped circuits generated simultaneously in very low CPU time. Our method has been automated and applied to a large set of asynchronous benchmarks and industrial circuits.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 1997 Jan 1|
|Event||Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong|
Duration: 1997 Jun 9 → 1997 Jun 12
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering