Integrated synthesis system for speed-independent asynchronous circuits

Jer Min Jou, Ren Der Chen, Ke Ming Lin

Research output: Contribution to journalConference article

2 Citations (Scopus)

Abstract

In this paper, an integrated synthesis system is established to synthesize speed-independent asynchronous circuits directly from STGs with limited fanin basic gates. It combines asynchronous technology mapping and synthesis into an integrated one and thus can get the mapping solution for those whose mapping results can not be generated by previous separate mapping methods. In addition, the whole synthesis is carried out entirely on the STG level without generating the SGs and thereby preserve the problem size proportional to the number of signals. With the proposed method, STGs can be synthesized and hazard-free mapped circuits generated simultaneously in very low CPU time. Our method has been automated and applied to a large set of asynchronous benchmarks and industrial circuits.

Original languageEnglish
Pages (from-to)1600-1603
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
Publication statusPublished - 1997 Jan 1
EventProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong
Duration: 1997 Jun 91997 Jun 12

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Networks (circuits)
Program processors
Hazards

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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Integrated synthesis system for speed-independent asynchronous circuits. / Jou, Jer Min; Chen, Ren Der; Lin, Ke Ming.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 3, 01.01.1997, p. 1600-1603.

Research output: Contribution to journalConference article

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