Input control technique for power reduction in scan circuits during test application

Tsung Chu Huang, Kuen Jong Lee

Research output: Contribution to journalConference article

32 Citations (Scopus)

Abstract

This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application. The basic idea is to identify an input control pattern for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be minimized or even eliminated. A D-algorithm-like pattern generator is developed to generate the control pattern. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve about 19.29% of average improvement, while 29.28% average improvement can be achieved if the input control technique is employed before the vector ordering and the latch ordering techniques.

Original languageEnglish
Pages (from-to)315-320
Number of pages6
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 1999 Dec 1
EventProceedings of the 1999 8th Asian Test Symposium (ATS'99) - Shanghai, China
Duration: 1999 Nov 161999 Nov 18

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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