Abstract
In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied by the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speeds up the clock rate of the DWT. The architecture is coded in Verilog HDL, implemented in a FPGA, and verified by the platform of Quartus-II which is a realtime platform comprising a CMOS image sensor, a FPGA and a TFT-LCD panel.
| Original language | English |
|---|---|
| Title of host publication | Second International Conference on Innovative Computing, Information and Control, ICICIC 2007 |
| Publisher | IEEE Computer Society |
| ISBN (Print) | 0769528821, 9780769528823 |
| DOIs | |
| Publication status | Published - 2007 Jan 1 |
| Event | 2nd International Conference on Innovative Computing, Information and Control, ICICIC 2007 - Kumamoto, Japan Duration: 2007 Sep 5 → 2007 Sep 7 |
Publication series
| Name | Second International Conference on Innovative Computing, Information and Control, ICICIC 2007 |
|---|
Other
| Other | 2nd International Conference on Innovative Computing, Information and Control, ICICIC 2007 |
|---|---|
| Country | Japan |
| City | Kumamoto |
| Period | 07-09-05 → 07-09-07 |
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All Science Journal Classification (ASJC) codes
- Mechanical Engineering
- Computer Science(all)
Cite this
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Implementation of an efficient DWT using a FPGA on a real-time platform. / Hsieh, Chin Fa; Tsai, Tsung Han; Lai, Chih Hung; Yi, Shu Chung; Yen, Mao Hsu.
Second International Conference on Innovative Computing, Information and Control, ICICIC 2007. IEEE Computer Society, 2007. 4427880 (Second International Conference on Innovative Computing, Information and Control, ICICIC 2007).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Implementation of an efficient DWT using a FPGA on a real-time platform
AU - Hsieh, Chin Fa
AU - Tsai, Tsung Han
AU - Lai, Chih Hung
AU - Yi, Shu Chung
AU - Yen, Mao Hsu
PY - 2007/1/1
Y1 - 2007/1/1
N2 - In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied by the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speeds up the clock rate of the DWT. The architecture is coded in Verilog HDL, implemented in a FPGA, and verified by the platform of Quartus-II which is a realtime platform comprising a CMOS image sensor, a FPGA and a TFT-LCD panel.
AB - In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied by the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speeds up the clock rate of the DWT. The architecture is coded in Verilog HDL, implemented in a FPGA, and verified by the platform of Quartus-II which is a realtime platform comprising a CMOS image sensor, a FPGA and a TFT-LCD panel.
UR - http://www.scopus.com/inward/record.url?scp=39049091967&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=39049091967&partnerID=8YFLogxK
U2 - 10.1109/ICICIC.2007.346
DO - 10.1109/ICICIC.2007.346
M3 - Conference contribution
AN - SCOPUS:39049091967
SN - 0769528821
SN - 9780769528823
T3 - Second International Conference on Innovative Computing, Information and Control, ICICIC 2007
BT - Second International Conference on Innovative Computing, Information and Control, ICICIC 2007
PB - IEEE Computer Society
ER -