Implementation of an efficient DWT using a FPGA on a real-time platform

Chin Fa Hsieh, Tsung Han Tsai, Chih Hung Lai, Shu Chung Yi, Mao Hsu Yen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied by the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speeds up the clock rate of the DWT. The architecture is coded in Verilog HDL, implemented in a FPGA, and verified by the platform of Quartus-II which is a realtime platform comprising a CMOS image sensor, a FPGA and a TFT-LCD panel.

Original languageEnglish
Title of host publicationSecond International Conference on Innovative Computing, Information and Control, ICICIC 2007
PublisherIEEE Computer Society
ISBN (Print)0769528821, 9780769528823
DOIs
Publication statusPublished - 2007 Jan 1
Event2nd International Conference on Innovative Computing, Information and Control, ICICIC 2007 - Kumamoto, Japan
Duration: 2007 Sep 52007 Sep 7

Publication series

NameSecond International Conference on Innovative Computing, Information and Control, ICICIC 2007

Other

Other2nd International Conference on Innovative Computing, Information and Control, ICICIC 2007
CountryJapan
CityKumamoto
Period07-09-0507-09-07

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All Science Journal Classification (ASJC) codes

  • Mechanical Engineering
  • Computer Science(all)

Cite this

Hsieh, C. F., Tsai, T. H., Lai, C. H., Yi, S. C., & Yen, M. H. (2007). Implementation of an efficient DWT using a FPGA on a real-time platform. In Second International Conference on Innovative Computing, Information and Control, ICICIC 2007 [4427880] (Second International Conference on Innovative Computing, Information and Control, ICICIC 2007). IEEE Computer Society. https://doi.org/10.1109/ICICIC.2007.346