HYPERA: High-yield performance-efficient redundancy analysis

Tsung Chu Huang; Kuei Yeh Lu; Yen Chieh Huang

doi:10.1109/ATS.2010.48

HYPERA: High-yield performance-efficient redundancy analysis

Tsung Chu Huang, Kuei Yeh Lu, Yen Chieh Huang

Department of Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A novel memory repair architecture based on redundant hypercube is proposed, which mainly consists of a modified ternary CAM with an address bubble-shifter. Generally for an acceptable repair rate about 3% of spare subcubes and no more than 5% of hardware overhead are required. A modified Quine-McCluskey algorithm and the Essential Cube Pivoting algorithm are also developed for redundancy analysis. Almost 100% of repair rate can be obtained using only 32 equivalent rows under reasonable situations. Under less spare memory the repair rates of proposed approaches can be much higher than most results of previous work.

Original language	English
Title of host publication	Proceedings - 2010 19th IEEE Asian Test Symposium, ATS 2010
Pages	231-236
Number of pages	6
DOIs	https://doi.org/10.1109/ATS.2010.48
Publication status	Published - 2010 Dec 1
Event	2010 19th IEEE Asian Test Symposium, ATS 2010 - Shanghai, China Duration: 2010 Dec 1 → 2010 Dec 4

Publication series

Name	Proceedings of the Asian Test Symposium
ISSN (Print)	1081-7735

Other

Other	2010 19th IEEE Asian Test Symposium, ATS 2010
Country	China
City	Shanghai
Period	10-12-01 → 10-12-04

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All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

Huang, T. C., Lu, K. Y., & Huang, Y. C. (2010). HYPERA: High-yield performance-efficient redundancy analysis. In Proceedings - 2010 19th IEEE Asian Test Symposium, ATS 2010 (pp. 231-236). [5692252] (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2010.48

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Access to Document

10.1109/ATS.2010.48