Hybrid stacking structure of electroplated copper onto graphene for future interconnect applications

Ya Wen Su, Cen-Shawn Wu, Chih Hua Liu, Hung Yi Lin, Chii Dong Chen

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

We show the feasibility of copper electroplating using graphene as a seed layer. Thermal annealing of the as-plated copper-graphene hybrid system promotes permeation of copper into graphene, forming an intermixing layer with enlarged lattice constant. It is shown that this intermixing layer blocks the diffusion of copper into the bottom SiO2/Si substrate at temperatures up to 900°C. The electroplating process is comparable with current semiconductor fabrication technology. This hybrid system can serve as interconnect in the integrated circuits.

Original languageEnglish
Article number093105
JournalApplied Physics Letters
Volume107
Issue number9
DOIs
Publication statusPublished - 2015 Aug 31

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graphene
copper
electroplating
integrated circuits
seeds
fabrication
annealing
temperature

All Science Journal Classification (ASJC) codes

  • Physics and Astronomy (miscellaneous)

Cite this

Su, Ya Wen ; Wu, Cen-Shawn ; Liu, Chih Hua ; Lin, Hung Yi ; Chen, Chii Dong. / Hybrid stacking structure of electroplated copper onto graphene for future interconnect applications. In: Applied Physics Letters. 2015 ; Vol. 107, No. 9.
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Hybrid stacking structure of electroplated copper onto graphene for future interconnect applications. / Su, Ya Wen; Wu, Cen-Shawn; Liu, Chih Hua; Lin, Hung Yi; Chen, Chii Dong.

In: Applied Physics Letters, Vol. 107, No. 9, 093105, 31.08.2015.

Research output: Contribution to journalArticle

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