Abstract
A 4×4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus multiplier is, respectively, less about 8.7% and 18% also.
| Original language | English |
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| Title of host publication | Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10 |
| Pages | 44-49 |
| Number of pages | 6 |
| Publication status | Published - 2010 Dec 1 |
| Event | 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10 - Hangzhou, China Duration: 2010 Apr 11 → 2010 Apr 13 |
Publication series
| Name | Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10 |
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Other
| Other | 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10 |
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| Country | China |
| City | Hangzhou |
| Period | 10-04-11 → 10-04-13 |
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All Science Journal Classification (ASJC) codes
- Computational Theory and Mathematics
- Computer Science Applications
Cite this
Lin, C. H., Yi, S. C., & Chen, J. J. (2010). High speed multiplier based on the algorithm of Chinese abacus. In Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10 (pp. 44-49). (Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10).