TY - GEN
T1 - High speed multiplier based on the algorithm of Chinese abacus
AU - Lin, Chien Hung
AU - Yi, Shu Chung
AU - Chen, Jin Jia
PY - 2010/12/1
Y1 - 2010/12/1
N2 - A 4×4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus multiplier is, respectively, less about 8.7% and 18% also.
AB - A 4×4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus multiplier is, respectively, less about 8.7% and 18% also.
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M3 - Conference contribution
AN - SCOPUS:79952554049
SN - 9789604741731
T3 - Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10
SP - 44
EP - 49
BT - Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10
T2 - 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10
Y2 - 11 April 2010 through 13 April 2010
ER -