### Abstract

A 4×4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus multiplier is, respectively, less about 8.7% and 18% also.

Original language | English |
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Title of host publication | Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10 |

Pages | 44-49 |

Number of pages | 6 |

Publication status | Published - 2010 Dec 1 |

Event | 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10 - Hangzhou, China Duration: 2010 Apr 11 → 2010 Apr 13 |

### Publication series

Name | Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10 |
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### Other

Other | 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10 |
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Country | China |

City | Hangzhou |

Period | 10-04-11 → 10-04-13 |

### Fingerprint

### All Science Journal Classification (ASJC) codes

- Computational Theory and Mathematics
- Computer Science Applications

### Cite this

*Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10*(pp. 44-49). (Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10).

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*Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10.*Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10, pp. 44-49, 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10, Hangzhou, China, 10-04-11.

**High speed multiplier based on the algorithm of Chinese abacus.** / Lin, Chien Hung; Yi, Shu Chung; Chen, Jin Jia.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - High speed multiplier based on the algorithm of Chinese abacus

AU - Lin, Chien Hung

AU - Yi, Shu Chung

AU - Chen, Jin Jia

PY - 2010/12/1

Y1 - 2010/12/1

N2 - A 4×4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus multiplier is, respectively, less about 8.7% and 18% also.

AB - A 4×4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus multiplier is, respectively, less about 8.7% and 18% also.

UR - http://www.scopus.com/inward/record.url?scp=79952554049&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79952554049&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:79952554049

SN - 9789604741731

T3 - Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10

SP - 44

EP - 49

BT - Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10

ER -