High speed multiplier based on the algorithm of Chinese abacus

Chien Hung Lin; Shu Chung Yi; Jin Jia Chen

High speed multiplier based on the algorithm of Chinese abacus

Chien Hung Lin, Shu Chung Yi, Jin Jia Chen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A 4×4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus multiplier is, respectively, less about 8.7% and 18% also.

Original language	English
Title of host publication	Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10
Pages	44-49
Number of pages	6
Publication status	Published - 2010 Dec 1
Event	9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10 - Hangzhou, China Duration: 2010 Apr 11 → 2010 Apr 13

Publication series

Name	Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10

Other

Other	9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10
Country	China
City	Hangzhou
Period	10-04-11 → 10-04-13

All Science Journal Classification (ASJC) codes

Computational Theory and Mathematics
Computer Science Applications

Access to Document

Fingerprint Dive into the research topics of 'High speed multiplier based on the algorithm of Chinese abacus'. Together they form a unique fingerprint.

Cite this

Lin, Chien Hung ; Yi, Shu Chung ; Chen, Jin Jia. / High speed multiplier based on the algorithm of Chinese abacus. Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10. 2010. pp. 44-49 (Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10).

@inproceedings{34b4100389784980b3c145e1392c8c28,

title = "High speed multiplier based on the algorithm of Chinese abacus",

abstract = "A 4×4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus multiplier is, respectively, less about 8.7% and 18% also.",

author = "Lin, {Chien Hung} and Yi, {Shu Chung} and Chen, {Jin Jia}",

year = "2010",

month = dec,

day = "1",

language = "English",

isbn = "9789604741731",

series = "Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10",

pages = "44--49",

booktitle = "Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10",

note = "9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10 ; Conference date: 11-04-2010 Through 13-04-2010",

}

Lin, CH, Yi, SC & Chen, JJ 2010, High speed multiplier based on the algorithm of Chinese abacus. in Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10. Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10, pp. 44-49, 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10, Hangzhou, China, 10-04-11.

High speed multiplier based on the algorithm of Chinese abacus. / Lin, Chien Hung; Yi, Shu Chung ; Chen, Jin Jia.

Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10. 2010. p. 44-49 (Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - High speed multiplier based on the algorithm of Chinese abacus

AU - Lin, Chien Hung

AU - Yi, Shu Chung

AU - Chen, Jin Jia

PY - 2010/12/1

Y1 - 2010/12/1

N2 - A 4×4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus multiplier is, respectively, less about 8.7% and 18% also.

AB - A 4×4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus multiplier is, respectively, less about 8.7% and 18% also.

UR - http://www.scopus.com/inward/record.url?scp=79952554049&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79952554049&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:79952554049

SN - 9789604741731

T3 - Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10

SP - 44

EP - 49

BT - Proceedings of the 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10

T2 - 9th WSEAS International Conference on Applied Computer and Applied Computational Science, ACACOS '10

Y2 - 11 April 2010 through 13 April 2010

ER -