High power CMOS power amplifier for WCDMA

Yu Chun Huang, Zhi-Ming Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper we propose a power amplifier (PA) for high output power and high linearity WCDMA applications. This PA is designed based on a three-stage configuration and an output stage designed by a multiple gated transistor topology. The test chip is simulated and fabricated with the TSMC 0.18μm CMOS process. Simulation results show that the power amplifier achieves 24.4 dB of power gain, 25 dBm of 1dB compression power output, and 27.6 dBm at third order output interception point (OIP3). The power added efficiency (PAE) at gain compression point is 33.5%. The die size is 1.2 × 1.2 mm2.

Original languageEnglish
Title of host publicationAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages199-202
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
EventAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
Duration: 2006 Dec 42006 Dec 6

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
CountrySingapore
Period06-12-0406-12-06

Fingerprint

Power amplifiers
Transistors
Topology

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Huang, Y. C., & Lin, Z-M. (2006). High power CMOS power amplifier for WCDMA. In APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (pp. 199-202). [4145365] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2006.342366
Huang, Yu Chun ; Lin, Zhi-Ming. / High power CMOS power amplifier for WCDMA. APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. pp. 199-202 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).
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abstract = "In this paper we propose a power amplifier (PA) for high output power and high linearity WCDMA applications. This PA is designed based on a three-stage configuration and an output stage designed by a multiple gated transistor topology. The test chip is simulated and fabricated with the TSMC 0.18μm CMOS process. Simulation results show that the power amplifier achieves 24.4 dB of power gain, 25 dBm of 1dB compression power output, and 27.6 dBm at third order output interception point (OIP3). The power added efficiency (PAE) at gain compression point is 33.5{\%}. The die size is 1.2 × 1.2 mm2.",
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Huang, YC & Lin, Z-M 2006, High power CMOS power amplifier for WCDMA. in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems., 4145365, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 199-202, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 06-12-04. https://doi.org/10.1109/APCCAS.2006.342366

High power CMOS power amplifier for WCDMA. / Huang, Yu Chun; Lin, Zhi-Ming.

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 199-202 4145365 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Huang YC, Lin Z-M. High power CMOS power amplifier for WCDMA. In APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 199-202. 4145365. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2006.342366