Abstract
In this reported work, a built-in self-routing scheme is developed for exploring the through-silicon via (TSV) redundancy to the extremes. A built-in self-router consists of a built-in self-tester for testing the TSVs, and a priority switching network for selecting from M TSVs to N inter-chip interconnects. A switching cell is developed to sequentially construct the priority switching network for area reduction and synthesis regularity. Although a long latency is needed for the encoding network, the best performance during inter-chip communication can be achieved due to only one switch per tier in normal operations. In a multiple fault model with no more than M-N defected TSVs, the repair rate can be always 100.
| Original language | English |
|---|---|
| Pages (from-to) | 480-482 |
| Number of pages | 3 |
| Journal | Electronics Letters |
| Volume | 48 |
| Issue number | 9 |
| DOIs | |
| Publication status | Published - 2012 Apr 26 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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High-performance built-in self-routing for through-silicon vias. / Huang, Tsung-Chu.
In: Electronics Letters, Vol. 48, No. 9, 26.04.2012, p. 480-482.Research output: Contribution to journal › Article
TY - JOUR
T1 - High-performance built-in self-routing for through-silicon vias
AU - Huang, Tsung-Chu
PY - 2012/4/26
Y1 - 2012/4/26
N2 - In this reported work, a built-in self-routing scheme is developed for exploring the through-silicon via (TSV) redundancy to the extremes. A built-in self-router consists of a built-in self-tester for testing the TSVs, and a priority switching network for selecting from M TSVs to N inter-chip interconnects. A switching cell is developed to sequentially construct the priority switching network for area reduction and synthesis regularity. Although a long latency is needed for the encoding network, the best performance during inter-chip communication can be achieved due to only one switch per tier in normal operations. In a multiple fault model with no more than M-N defected TSVs, the repair rate can be always 100.
AB - In this reported work, a built-in self-routing scheme is developed for exploring the through-silicon via (TSV) redundancy to the extremes. A built-in self-router consists of a built-in self-tester for testing the TSVs, and a priority switching network for selecting from M TSVs to N inter-chip interconnects. A switching cell is developed to sequentially construct the priority switching network for area reduction and synthesis regularity. Although a long latency is needed for the encoding network, the best performance during inter-chip communication can be achieved due to only one switch per tier in normal operations. In a multiple fault model with no more than M-N defected TSVs, the repair rate can be always 100.
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U2 - 10.1049/el.2012.0286
DO - 10.1049/el.2012.0286
M3 - Article
VL - 48
SP - 480
EP - 482
JO - Electronics Letters
JF - Electronics Letters
SN - 0013-5194
IS - 9
ER -