Hardware implementation for a genetic algorithm

Pei Yin Chen, Ren-Der Chen, Yu Pin Chang, Leang San Shieh, H. A. Malki

Research output: Contribution to journalArticle

23 Citations (Scopus)

Abstract

A genetic algorithm (GA) can find an optimal solution in many complex problems. GAs have been widely used in many applications. A flexible-very-large-scale integration intellectual property for the GA has been proposed in this paper. This algorithm can dynamically perform various population sizes, fitness lengths, individual lengths, fitness functions, crossover operations, and mutation-rate settings to meet the real-time requirements of various GA applications. It can be seen from the simulation results that our design works very well for the three examples running at an 83-MHz clock frequency.

Original languageEnglish
Pages (from-to)699-705
Number of pages7
JournalIEEE Transactions on Instrumentation and Measurement
Volume57
Issue number4
DOIs
Publication statusPublished - 2008 Apr 1

Fingerprint

genetic algorithms
hardware
fitness
Genetic algorithms
Hardware
intellectual property
VLSI circuits
Intellectual property
very large scale integration
mutations
clocks
Clocks
crossovers
requirements
simulation

All Science Journal Classification (ASJC) codes

  • Instrumentation
  • Electrical and Electronic Engineering

Cite this

Chen, Pei Yin ; Chen, Ren-Der ; Chang, Yu Pin ; Shieh, Leang San ; Malki, H. A. / Hardware implementation for a genetic algorithm. In: IEEE Transactions on Instrumentation and Measurement. 2008 ; Vol. 57, No. 4. pp. 699-705.
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Hardware implementation for a genetic algorithm. / Chen, Pei Yin; Chen, Ren-Der; Chang, Yu Pin; Shieh, Leang San; Malki, H. A.

In: IEEE Transactions on Instrumentation and Measurement, Vol. 57, No. 4, 01.04.2008, p. 699-705.

Research output: Contribution to journalArticle

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