@inproceedings{48abf07c652b4787a422d5963fd93692,
title = "Hardware accelerator for boosting convolution computation in image classification applications",
abstract = "In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).",
author = "Chang, {Meng Chou} and Pan, {Ze Gang} and Chen, {Jyun Liang}",
year = "2017",
month = dec,
day = "19",
doi = "10.1109/GCCE.2017.8229395",
language = "English",
series = "2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017",
address = "United States",
note = "6th IEEE Global Conference on Consumer Electronics, GCCE 2017 ; Conference date: 24-10-2017 Through 27-10-2017",
}