Hardware accelerator for boosting convolution computation in image classification applications

Meng Chou Chang, Ze Gang Pan, Jyun Liang Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).

Original languageEnglish
Title of host publication2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509040452
DOIs
Publication statusPublished - 2017 Dec 19
Event6th IEEE Global Conference on Consumer Electronics, GCCE 2017 - Nagoya, Japan
Duration: 2017 Oct 242017 Oct 27

Publication series

Name2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017
Volume2017-January

Other

Other6th IEEE Global Conference on Consumer Electronics, GCCE 2017
CountryJapan
CityNagoya
Period17-10-2417-10-27

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All Science Journal Classification (ASJC) codes

  • Media Technology
  • Instrumentation
  • Electrical and Electronic Engineering

Cite this

Chang, M. C., Pan, Z. G., & Chen, J. L. (2017). Hardware accelerator for boosting convolution computation in image classification applications. In 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017 (2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017; Vol. 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/GCCE.2017.8229395