Abstract
In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).
| Original language | English |
|---|---|
| Title of host publication | 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781509040452 |
| DOIs | |
| Publication status | Published - 2017 Dec 19 |
| Event | 6th IEEE Global Conference on Consumer Electronics, GCCE 2017 - Nagoya, Japan Duration: 2017 Oct 24 → 2017 Oct 27 |
Publication series
| Name | 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017 |
|---|---|
| Volume | 2017-January |
Other
| Other | 6th IEEE Global Conference on Consumer Electronics, GCCE 2017 |
|---|---|
| Country | Japan |
| City | Nagoya |
| Period | 17-10-24 → 17-10-27 |
All Science Journal Classification (ASJC) codes
- Media Technology
- Instrumentation
- Electrical and Electronic Engineering
Fingerprint Dive into the research topics of 'Hardware accelerator for boosting convolution computation in image classification applications'. Together they form a unique fingerprint.
Cite this
Chang, M. C., Pan, Z. G., & Chen, J. L. (2017). Hardware accelerator for boosting convolution computation in image classification applications. In 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017 (2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017; Vol. 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/GCCE.2017.8229395