Abstract
In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).
| Original language | English |
|---|---|
| Title of host publication | 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781509040452 |
| DOIs | |
| Publication status | Published - 2017 Dec 19 |
| Event | 6th IEEE Global Conference on Consumer Electronics, GCCE 2017 - Nagoya, Japan Duration: 2017 Oct 24 → 2017 Oct 27 |
Publication series
| Name | 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017 |
|---|---|
| Volume | 2017-January |
Other
| Other | 6th IEEE Global Conference on Consumer Electronics, GCCE 2017 |
|---|---|
| Country | Japan |
| City | Nagoya |
| Period | 17-10-24 → 17-10-27 |
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All Science Journal Classification (ASJC) codes
- Media Technology
- Instrumentation
- Electrical and Electronic Engineering
Cite this
}
Hardware accelerator for boosting convolution computation in image classification applications. / Chang, Meng Chou; Pan, Ze Gang; Chen, Jyun Liang.
2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. Institute of Electrical and Electronics Engineers Inc., 2017. (2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017; Vol. 2017-January).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Hardware accelerator for boosting convolution computation in image classification applications
AU - Chang, Meng Chou
AU - Pan, Ze Gang
AU - Chen, Jyun Liang
PY - 2017/12/19
Y1 - 2017/12/19
N2 - In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).
AB - In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).
UR - http://www.scopus.com/inward/record.url?scp=85045731495&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85045731495&partnerID=8YFLogxK
U2 - 10.1109/GCCE.2017.8229395
DO - 10.1109/GCCE.2017.8229395
M3 - Conference contribution
AN - SCOPUS:85045731495
T3 - 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017
BT - 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017
PB - Institute of Electrical and Electronics Engineers Inc.
ER -