Hardware accelerator for boosting convolution computation in image classification applications

Meng Chou Chang; Ze Gang Pan; Jyun Liang Chen

doi:10.1109/GCCE.2017.8229395

Hardware accelerator for boosting convolution computation in image classification applications

Meng Chou Chang, Ze Gang Pan, Jyun Liang Chen

Department of Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).

Original language	English
Title of host publication	2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509040452
DOIs	https://doi.org/10.1109/GCCE.2017.8229395
Publication status	Published - 2017 Dec 19
Event	6th IEEE Global Conference on Consumer Electronics, GCCE 2017 - Nagoya, Japan Duration: 2017 Oct 24 → 2017 Oct 27

Publication series

Name	2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017
Volume	2017-January

Other

Other	6th IEEE Global Conference on Consumer Electronics, GCCE 2017
Country	Japan
City	Nagoya
Period	17-10-24 → 17-10-27

Fingerprint

All Science Journal Classification (ASJC) codes

Media Technology
Instrumentation
Electrical and Electronic Engineering

Cite this

Chang, M. C., Pan, Z. G., & Chen, J. L. (2017). Hardware accelerator for boosting convolution computation in image classification applications. In 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017 (2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017; Vol. 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/GCCE.2017.8229395

@inproceedings{48abf07c652b4787a422d5963fd93692,

title = "Hardware accelerator for boosting convolution computation in image classification applications",

abstract = "In a convolutional neural network (CNN), convolution calculation can account for about 90{\%} of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).",

author = "Chang, {Meng Chou} and Pan, {Ze Gang} and Chen, {Jyun Liang}",

year = "2017",

month = "12",

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doi = "10.1109/GCCE.2017.8229395",

language = "English",

series = "2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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note = "6th IEEE Global Conference on Consumer Electronics, GCCE 2017 ; Conference date: 24-10-2017 Through 27-10-2017",

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Chang, MC, Pan, ZG & Chen, JL 2017, Hardware accelerator for boosting convolution computation in image classification applications. in 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017, vol. 2017-January, Institute of Electrical and Electronics Engineers Inc., 6th IEEE Global Conference on Consumer Electronics, GCCE 2017, Nagoya, Japan, 17-10-24. https://doi.org/10.1109/GCCE.2017.8229395

Hardware accelerator for boosting convolution computation in image classification applications. / Chang, Meng Chou; Pan, Ze Gang; Chen, Jyun Liang.

2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. Institute of Electrical and Electronics Engineers Inc., 2017. (2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017; Vol. 2017-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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PY - 2017/12/19

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N2 - In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).

AB - In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).

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Access to Document

10.1109/GCCE.2017.8229395