Grouping memory consistency model for parallel-multithreaded shared-memory multiprocessor systems

Chao Chin Wu, Cheng Chen

Research output: Contribution to journalArticle

Abstract

In this paper, we propose a hardware-centric memory consistency model particularly for shared-memory multiprocessors with parallel-multithreaded processing elements. According to the behavior of critical sections and the feature of parallel-multithreaded processors, we extend the release consistency model to a more relaxed memory model. A release reference at the end of a critical section can be executed locally regardless of whether all of its previous ordinary references have performed. The requirement is that another thread on the same processor is waiting for the lock to be freed. Two new instructions and two additional macros are needed to properly label a program for our proposed model. Moreover, we use a table per processing element to determine if there are any threads waiting for a specific lock. We have used five benchmark programs in the SPLASH suite to evaluate the performance gain for the new model. According to the simulation results, our proposed model is superior to the release consistency model up to 25%.

Original languageEnglish
Pages (from-to)53-81
Number of pages29
JournalInternational Journal of High Speed Computing
Volume10
Issue number1
DOIs
Publication statusPublished - 1999 Mar

Fingerprint

Shared-memory multiprocessors
Multiprocessor Systems
Grouping
Computer systems
Data storage equipment
Thread
Model
Parallel Processors
Memory Model
Parallel Processing
Processing
Table
Computer hardware
Macros
Labels
Hardware
Benchmark
Evaluate
Requirements
Simulation

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computational Theory and Mathematics

Cite this

@article{099f049fe73e43aaad9dc453db236f70,
title = "Grouping memory consistency model for parallel-multithreaded shared-memory multiprocessor systems",
abstract = "In this paper, we propose a hardware-centric memory consistency model particularly for shared-memory multiprocessors with parallel-multithreaded processing elements. According to the behavior of critical sections and the feature of parallel-multithreaded processors, we extend the release consistency model to a more relaxed memory model. A release reference at the end of a critical section can be executed locally regardless of whether all of its previous ordinary references have performed. The requirement is that another thread on the same processor is waiting for the lock to be freed. Two new instructions and two additional macros are needed to properly label a program for our proposed model. Moreover, we use a table per processing element to determine if there are any threads waiting for a specific lock. We have used five benchmark programs in the SPLASH suite to evaluate the performance gain for the new model. According to the simulation results, our proposed model is superior to the release consistency model up to 25{\%}.",
author = "Wu, {Chao Chin} and Cheng Chen",
year = "1999",
month = "3",
doi = "10.1142/S0129053399000041",
language = "English",
volume = "10",
pages = "53--81",
journal = "International Journal of High Speed Computing",
issn = "0129-0533",
publisher = "World Scientific Publishing Co. Pte Ltd",
number = "1",

}

Grouping memory consistency model for parallel-multithreaded shared-memory multiprocessor systems. / Wu, Chao Chin; Chen, Cheng.

In: International Journal of High Speed Computing, Vol. 10, No. 1, 03.1999, p. 53-81.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Grouping memory consistency model for parallel-multithreaded shared-memory multiprocessor systems

AU - Wu, Chao Chin

AU - Chen, Cheng

PY - 1999/3

Y1 - 1999/3

N2 - In this paper, we propose a hardware-centric memory consistency model particularly for shared-memory multiprocessors with parallel-multithreaded processing elements. According to the behavior of critical sections and the feature of parallel-multithreaded processors, we extend the release consistency model to a more relaxed memory model. A release reference at the end of a critical section can be executed locally regardless of whether all of its previous ordinary references have performed. The requirement is that another thread on the same processor is waiting for the lock to be freed. Two new instructions and two additional macros are needed to properly label a program for our proposed model. Moreover, we use a table per processing element to determine if there are any threads waiting for a specific lock. We have used five benchmark programs in the SPLASH suite to evaluate the performance gain for the new model. According to the simulation results, our proposed model is superior to the release consistency model up to 25%.

AB - In this paper, we propose a hardware-centric memory consistency model particularly for shared-memory multiprocessors with parallel-multithreaded processing elements. According to the behavior of critical sections and the feature of parallel-multithreaded processors, we extend the release consistency model to a more relaxed memory model. A release reference at the end of a critical section can be executed locally regardless of whether all of its previous ordinary references have performed. The requirement is that another thread on the same processor is waiting for the lock to be freed. Two new instructions and two additional macros are needed to properly label a program for our proposed model. Moreover, we use a table per processing element to determine if there are any threads waiting for a specific lock. We have used five benchmark programs in the SPLASH suite to evaluate the performance gain for the new model. According to the simulation results, our proposed model is superior to the release consistency model up to 25%.

UR - http://www.scopus.com/inward/record.url?scp=8344219826&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=8344219826&partnerID=8YFLogxK

U2 - 10.1142/S0129053399000041

DO - 10.1142/S0129053399000041

M3 - Article

AN - SCOPUS:8344219826

VL - 10

SP - 53

EP - 81

JO - International Journal of High Speed Computing

JF - International Journal of High Speed Computing

SN - 0129-0533

IS - 1

ER -