Exploiting instruction-level parallelism with the conjugate register file scheme

Meng chou Chang; Feipei Lai; Rung ji Shang

doi:10.1145/144965.144986

Exploiting instruction-level parallelism with the conjugate register file scheme

Meng chou Chang, Feipei Lai, Rung ji Shang

Department of Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper proposes a new micro-architecture, called IAS-S, which takes advantage of the Conjugate Register File (CRF) scheme to support speculative execution, such as multi-level boosting and multi-way branch, without incurring excessive hardware overhead. A software technique which integrates register allocation and instruction scheduling has been developed to exploit the conjugate register file. The scheduling-conflict graph is built before the starting of register allocation so that the ability of the instruction scheduler to optimize the instruction sequence will not be severely restricted by the reuse of registers.

Original language	English
Title of host publication	Proceedings of the 25th Annual International Symposium on Microarchitecture
Publisher	Publ by ACM
Pages	29-32
Number of pages	4
ISBN (Print)	0818631759, 9780818631757
DOIs	https://doi.org/10.1145/144965.144986
Publication status	Published - 1992
Event	Proceedings of the 25th Annual International Symposium on Microarchitecture - Portland, OR, USA Duration: 1992 Dec 1 → 1992 Dec 4

Publication series

Name	Proceedings of the 25th Annual International Symposium on Microarchitecture

Other

Other	Proceedings of the 25th Annual International Symposium on Microarchitecture
City	Portland, OR, USA
Period	92-12-01 → 92-12-04

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1145/144965.144986

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Cite this

@inproceedings{27abbe35f89c4beba3f0c5dcf9bd86ed,

title = "Exploiting instruction-level parallelism with the conjugate register file scheme",

abstract = "This paper proposes a new micro-architecture, called IAS-S, which takes advantage of the Conjugate Register File (CRF) scheme to support speculative execution, such as multi-level boosting and multi-way branch, without incurring excessive hardware overhead. A software technique which integrates register allocation and instruction scheduling has been developed to exploit the conjugate register file. The scheduling-conflict graph is built before the starting of register allocation so that the ability of the instruction scheduler to optimize the instruction sequence will not be severely restricted by the reuse of registers.",

author = "Chang, {Meng chou} and Feipei Lai and Shang, {Rung ji}",

year = "1992",

doi = "10.1145/144965.144986",

language = "English",

isbn = "0818631759",

series = "Proceedings of the 25th Annual International Symposium on Microarchitecture",

publisher = "Publ by ACM",

pages = "29--32",

booktitle = "Proceedings of the 25th Annual International Symposium on Microarchitecture",

note = "Proceedings of the 25th Annual International Symposium on Microarchitecture ; Conference date: 01-12-1992 Through 04-12-1992",

}

Chang, MC, Lai, F & Shang, RJ 1992, Exploiting instruction-level parallelism with the conjugate register file scheme. in Proceedings of the 25th Annual International Symposium on Microarchitecture. Proceedings of the 25th Annual International Symposium on Microarchitecture, Publ by ACM, pp. 29-32, Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, OR, USA, 92-12-01. https://doi.org/10.1145/144965.144986

Exploiting instruction-level parallelism with the conjugate register file scheme. / Chang, Meng chou; Lai, Feipei; Shang, Rung ji.

Proceedings of the 25th Annual International Symposium on Microarchitecture. Publ by ACM, 1992. p. 29-32 (Proceedings of the 25th Annual International Symposium on Microarchitecture).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Exploiting instruction-level parallelism with the conjugate register file scheme

AU - Chang, Meng chou

AU - Lai, Feipei

AU - Shang, Rung ji

PY - 1992

Y1 - 1992

N2 - This paper proposes a new micro-architecture, called IAS-S, which takes advantage of the Conjugate Register File (CRF) scheme to support speculative execution, such as multi-level boosting and multi-way branch, without incurring excessive hardware overhead. A software technique which integrates register allocation and instruction scheduling has been developed to exploit the conjugate register file. The scheduling-conflict graph is built before the starting of register allocation so that the ability of the instruction scheduler to optimize the instruction sequence will not be severely restricted by the reuse of registers.

AB - This paper proposes a new micro-architecture, called IAS-S, which takes advantage of the Conjugate Register File (CRF) scheme to support speculative execution, such as multi-level boosting and multi-way branch, without incurring excessive hardware overhead. A software technique which integrates register allocation and instruction scheduling has been developed to exploit the conjugate register file. The scheduling-conflict graph is built before the starting of register allocation so that the ability of the instruction scheduler to optimize the instruction sequence will not be severely restricted by the reuse of registers.

UR - http://www.scopus.com/inward/record.url?scp=0027001351&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027001351&partnerID=8YFLogxK

U2 - 10.1145/144965.144986

DO - 10.1145/144965.144986

M3 - Conference contribution

AN - SCOPUS:0027001351

SN - 0818631759

SN - 9780818631757

T3 - Proceedings of the 25th Annual International Symposium on Microarchitecture

SP - 29

EP - 32

BT - Proceedings of the 25th Annual International Symposium on Microarchitecture

PB - Publ by ACM

T2 - Proceedings of the 25th Annual International Symposium on Microarchitecture

Y2 - 1 December 1992 through 4 December 1992

ER -