Exploiting instruction-level parallelism with the conjugate register file scheme

Meng-Chou Chang, Feipei Lai, Rung ji Shang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper proposes a new micro-architecture, called IAS-S, which takes advantage of the Conjugate Register File (CRF) scheme to support speculative execution, such as multi-level boosting and multi-way branch, without incurring excessive hardware overhead. A software technique which integrates register allocation and instruction scheduling has been developed to exploit the conjugate register file. The scheduling-conflict graph is built before the starting of register allocation so that the ability of the instruction scheduler to optimize the instruction sequence will not be severely restricted by the reuse of registers.

Original languageEnglish
Title of host publicationProceedings of the 25th Annual International Symposium on Microarchitecture
PublisherPubl by ACM
Pages29-32
Number of pages4
ISBN (Print)0818631759
Publication statusPublished - 1992 Dec 1
EventProceedings of the 25th Annual International Symposium on Microarchitecture - Portland, OR, USA
Duration: 1992 Dec 11992 Dec 4

Publication series

NameProceedings of the 25th Annual International Symposium on Microarchitecture

Other

OtherProceedings of the 25th Annual International Symposium on Microarchitecture
CityPortland, OR, USA
Period92-12-0192-12-04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Chang, M-C., Lai, F., & Shang, R. J. (1992). Exploiting instruction-level parallelism with the conjugate register file scheme. In Proceedings of the 25th Annual International Symposium on Microarchitecture (pp. 29-32). (Proceedings of the 25th Annual International Symposium on Microarchitecture). Publ by ACM.