TY - GEN
T1 - Exploiting instruction-level parallelism with the conjugate register file scheme
AU - Chang, Meng chou
AU - Lai, Feipei
AU - Shang, Rung ji
PY - 1992
Y1 - 1992
N2 - This paper proposes a new micro-architecture, called IAS-S, which takes advantage of the Conjugate Register File (CRF) scheme to support speculative execution, such as multi-level boosting and multi-way branch, without incurring excessive hardware overhead. A software technique which integrates register allocation and instruction scheduling has been developed to exploit the conjugate register file. The scheduling-conflict graph is built before the starting of register allocation so that the ability of the instruction scheduler to optimize the instruction sequence will not be severely restricted by the reuse of registers.
AB - This paper proposes a new micro-architecture, called IAS-S, which takes advantage of the Conjugate Register File (CRF) scheme to support speculative execution, such as multi-level boosting and multi-way branch, without incurring excessive hardware overhead. A software technique which integrates register allocation and instruction scheduling has been developed to exploit the conjugate register file. The scheduling-conflict graph is built before the starting of register allocation so that the ability of the instruction scheduler to optimize the instruction sequence will not be severely restricted by the reuse of registers.
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U2 - 10.1145/144965.144986
DO - 10.1145/144965.144986
M3 - Conference contribution
AN - SCOPUS:0027001351
SN - 0818631759
SN - 9780818631757
T3 - Proceedings of the 25th Annual International Symposium on Microarchitecture
SP - 29
EP - 32
BT - Proceedings of the 25th Annual International Symposium on Microarchitecture
PB - Publ by ACM
T2 - Proceedings of the 25th Annual International Symposium on Microarchitecture
Y2 - 1 December 1992 through 4 December 1992
ER -