Abstract
This paper proposes a new micro-architecture, called IAS-S, which takes advantage of the Conjugate Register File (CRF) scheme to support speculative execution, such as multi-level boosting and multi-way branch, without incurring excessive hardware overhead. A software technique which integrates register allocation and instruction scheduling has been developed to exploit the conjugate register file. The scheduling-conflict graph is built before the starting of register allocation so that the ability of the instruction scheduler to optimize the instruction sequence will not be severely restricted by the reuse of registers.
| Original language | English |
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| Title of host publication | Proceedings of the 25th Annual International Symposium on Microarchitecture |
| Publisher | Publ by ACM |
| Pages | 29-32 |
| Number of pages | 4 |
| ISBN (Print) | 0818631759 |
| Publication status | Published - 1992 Dec 1 |
| Event | Proceedings of the 25th Annual International Symposium on Microarchitecture - Portland, OR, USA Duration: 1992 Dec 1 → 1992 Dec 4 |
Publication series
| Name | Proceedings of the 25th Annual International Symposium on Microarchitecture |
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Other
| Other | Proceedings of the 25th Annual International Symposium on Microarchitecture |
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| City | Portland, OR, USA |
| Period | 92-12-01 → 92-12-04 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
Cite this
Chang, M-C., Lai, F., & Shang, R. J. (1992). Exploiting instruction-level parallelism with the conjugate register file scheme. In Proceedings of the 25th Annual International Symposium on Microarchitecture (pp. 29-32). (Proceedings of the 25th Annual International Symposium on Microarchitecture). Publ by ACM.