TY - GEN
T1 - Enhancing boosting with semantic register in a superscalar processor
AU - Lai, Feipei
AU - Chang, Meng Chou
PY - 1993/12/1
Y1 - 1993/12/1
N2 - IAS-S Supports boosting with 'semantic register' and boosting boundary register to remove the dependences caused by conditional branches. In IAS-S, there is no dedicated shadow register file, and multiple levels of boosting is supported without multiple copies of register files. Any general-purpose register in IAS-S can be regarded as a sequential register or a shadow register flexibly. Furthermore, multi-way jump mechanism is combined with boosting to reduce the penalty due to frequent control transfers.
AB - IAS-S Supports boosting with 'semantic register' and boosting boundary register to remove the dependences caused by conditional branches. In IAS-S, there is no dedicated shadow register file, and multiple levels of boosting is supported without multiple copies of register files. Any general-purpose register in IAS-S can be regarded as a sequential register or a shadow register flexibly. Furthermore, multi-way jump mechanism is combined with boosting to reduce the penalty due to frequent control transfers.
UR - http://www.scopus.com/inward/record.url?scp=0027837795&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0027837795&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0027837795
SN - 0897915097
T3 - Proceedings of the Ninth Annual International Symposium on Computer Architecture
BT - Proceedings of the Ninth Annual International Symposium on Computer Architecture
PB - Publ by ACM
T2 - Proceedings of the 19th Annual International Symposium on Compu- ter Architecture
Y2 - 19 May 1992 through 21 May 1992
ER -