Abstract
This paper presents a time and area efficient method for the decomposition and resynthesis of speed-independent circuits from the signal transition graph (STG) specification. Our method first investigates the hazard-free decomposition of all high-fanin gates without adding any signals to the original specification. For those gates that can not be hazard-freely decomposed, we propose new signal-adding methods for resynthesis. Our decomposition and resynthesis techniques have been fully automated and applied to several asynchronous benchmarks. Compared with previous work, our method lowers the run time by 1-2 orders to magnitude, and the implementation area is also reduced.
| Original language | English |
|---|---|
| Pages (from-to) | 62-65 |
| Number of pages | 4 |
| Journal | International Symposium on VLSI Technology, Systems, and Applications, Proceedings |
| Publication status | Published - 1999 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)