Efficient method for the decomposition and resynthesis of speed-independent circuits

Ren-Der Chen, Jer Min Jou

Research output: Contribution to journalArticle

Abstract

This paper presents a time and area efficient method for the decomposition and resynthesis of speed-independent circuits from the signal transition graph (STG) specification. Our method first investigates the hazard-free decomposition of all high-fanin gates without adding any signals to the original specification. For those gates that can not be hazard-freely decomposed, we propose new signal-adding methods for resynthesis. Our decomposition and resynthesis techniques have been fully automated and applied to several asynchronous benchmarks. Compared with previous work, our method lowers the run time by 1-2 orders to magnitude, and the implementation area is also reduced.

Original languageEnglish
Pages (from-to)62-65
Number of pages4
JournalInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
Publication statusPublished - 1999 Jan 1

Fingerprint

Decomposition
decomposition
hazards
Networks (circuits)
specifications
Hazards
Specifications

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

@article{5a932599e11b403abec2d5a7006b36d8,
title = "Efficient method for the decomposition and resynthesis of speed-independent circuits",
abstract = "This paper presents a time and area efficient method for the decomposition and resynthesis of speed-independent circuits from the signal transition graph (STG) specification. Our method first investigates the hazard-free decomposition of all high-fanin gates without adding any signals to the original specification. For those gates that can not be hazard-freely decomposed, we propose new signal-adding methods for resynthesis. Our decomposition and resynthesis techniques have been fully automated and applied to several asynchronous benchmarks. Compared with previous work, our method lowers the run time by 1-2 orders to magnitude, and the implementation area is also reduced.",
author = "Ren-Der Chen and Jou, {Jer Min}",
year = "1999",
month = "1",
day = "1",
language = "English",
pages = "62--65",
journal = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",
issn = "1524-766X",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Efficient method for the decomposition and resynthesis of speed-independent circuits

AU - Chen, Ren-Der

AU - Jou, Jer Min

PY - 1999/1/1

Y1 - 1999/1/1

N2 - This paper presents a time and area efficient method for the decomposition and resynthesis of speed-independent circuits from the signal transition graph (STG) specification. Our method first investigates the hazard-free decomposition of all high-fanin gates without adding any signals to the original specification. For those gates that can not be hazard-freely decomposed, we propose new signal-adding methods for resynthesis. Our decomposition and resynthesis techniques have been fully automated and applied to several asynchronous benchmarks. Compared with previous work, our method lowers the run time by 1-2 orders to magnitude, and the implementation area is also reduced.

AB - This paper presents a time and area efficient method for the decomposition and resynthesis of speed-independent circuits from the signal transition graph (STG) specification. Our method first investigates the hazard-free decomposition of all high-fanin gates without adding any signals to the original specification. For those gates that can not be hazard-freely decomposed, we propose new signal-adding methods for resynthesis. Our decomposition and resynthesis techniques have been fully automated and applied to several asynchronous benchmarks. Compared with previous work, our method lowers the run time by 1-2 orders to magnitude, and the implementation area is also reduced.

UR - http://www.scopus.com/inward/record.url?scp=0032599263&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032599263&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0032599263

SP - 62

EP - 65

JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

SN - 1524-766X

ER -