Dynamic pipeline design of an adaptive binary arithmetic coder

Shiann Rong Kuang, Jer Min Jou, Ren-Der Chen, Yeu Horng Shiau

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

Arithmetic coding is an attractive technique for loss-less data compression but it tends to be slow. In this paper, a dynamic pipelined very large scale integration architecture with high performance for on-line adaptive binary arithmetic coding is presented. To obtain a high throughput pipelined architecture, we first analyze the computation flow of the coding algorithm and modify the operations whose data and/or control dependencies cause the difficulties in pipelining. Then, a novel technique called dynamic pipelining is developed to pipeline the coding process with variant (or run-time determined) pipeline latencies (or data initialization intervals) efficiently. As for data path design, a systematic design methodology of high level synthesis and a less-area but faster fixed-width multiplier are applied, which make the architecture with a little additional hardware. The dynamic pipelined architecture has been designed and simulated in Verilog HDL, and its layout has also been implemented with the 0.8μm SPDM CMOS process and the ITRI-CCL cell library. Its simulated compression speeds under working frequencies of 25 and 50 MHz are about 6 and 12.5 Mb/s, respectively. About two times the speedup with 30% hardware overhead relative to the original sequential one is achieved.

Original languageEnglish
Pages (from-to)813-825
Number of pages13
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume48
Issue number9
DOIs
Publication statusPublished - 2001 Sep 1

Fingerprint

Pipelines
Hardware
Computer hardware description languages
VLSI circuits
Data compression
Throughput
High level synthesis

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Electrical and Electronic Engineering

Cite this

@article{613a06ba3d4c4f94943d7e2234ee595f,
title = "Dynamic pipeline design of an adaptive binary arithmetic coder",
abstract = "Arithmetic coding is an attractive technique for loss-less data compression but it tends to be slow. In this paper, a dynamic pipelined very large scale integration architecture with high performance for on-line adaptive binary arithmetic coding is presented. To obtain a high throughput pipelined architecture, we first analyze the computation flow of the coding algorithm and modify the operations whose data and/or control dependencies cause the difficulties in pipelining. Then, a novel technique called dynamic pipelining is developed to pipeline the coding process with variant (or run-time determined) pipeline latencies (or data initialization intervals) efficiently. As for data path design, a systematic design methodology of high level synthesis and a less-area but faster fixed-width multiplier are applied, which make the architecture with a little additional hardware. The dynamic pipelined architecture has been designed and simulated in Verilog HDL, and its layout has also been implemented with the 0.8μm SPDM CMOS process and the ITRI-CCL cell library. Its simulated compression speeds under working frequencies of 25 and 50 MHz are about 6 and 12.5 Mb/s, respectively. About two times the speedup with 30{\%} hardware overhead relative to the original sequential one is achieved.",
author = "Kuang, {Shiann Rong} and Jou, {Jer Min} and Ren-Der Chen and Shiau, {Yeu Horng}",
year = "2001",
month = "9",
day = "1",
doi = "10.1109/82.964994",
language = "English",
volume = "48",
pages = "813--825",
journal = "IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing",
issn = "1057-7130",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "9",

}

Dynamic pipeline design of an adaptive binary arithmetic coder. / Kuang, Shiann Rong; Jou, Jer Min; Chen, Ren-Der; Shiau, Yeu Horng.

In: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 48, No. 9, 01.09.2001, p. 813-825.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Dynamic pipeline design of an adaptive binary arithmetic coder

AU - Kuang, Shiann Rong

AU - Jou, Jer Min

AU - Chen, Ren-Der

AU - Shiau, Yeu Horng

PY - 2001/9/1

Y1 - 2001/9/1

N2 - Arithmetic coding is an attractive technique for loss-less data compression but it tends to be slow. In this paper, a dynamic pipelined very large scale integration architecture with high performance for on-line adaptive binary arithmetic coding is presented. To obtain a high throughput pipelined architecture, we first analyze the computation flow of the coding algorithm and modify the operations whose data and/or control dependencies cause the difficulties in pipelining. Then, a novel technique called dynamic pipelining is developed to pipeline the coding process with variant (or run-time determined) pipeline latencies (or data initialization intervals) efficiently. As for data path design, a systematic design methodology of high level synthesis and a less-area but faster fixed-width multiplier are applied, which make the architecture with a little additional hardware. The dynamic pipelined architecture has been designed and simulated in Verilog HDL, and its layout has also been implemented with the 0.8μm SPDM CMOS process and the ITRI-CCL cell library. Its simulated compression speeds under working frequencies of 25 and 50 MHz are about 6 and 12.5 Mb/s, respectively. About two times the speedup with 30% hardware overhead relative to the original sequential one is achieved.

AB - Arithmetic coding is an attractive technique for loss-less data compression but it tends to be slow. In this paper, a dynamic pipelined very large scale integration architecture with high performance for on-line adaptive binary arithmetic coding is presented. To obtain a high throughput pipelined architecture, we first analyze the computation flow of the coding algorithm and modify the operations whose data and/or control dependencies cause the difficulties in pipelining. Then, a novel technique called dynamic pipelining is developed to pipeline the coding process with variant (or run-time determined) pipeline latencies (or data initialization intervals) efficiently. As for data path design, a systematic design methodology of high level synthesis and a less-area but faster fixed-width multiplier are applied, which make the architecture with a little additional hardware. The dynamic pipelined architecture has been designed and simulated in Verilog HDL, and its layout has also been implemented with the 0.8μm SPDM CMOS process and the ITRI-CCL cell library. Its simulated compression speeds under working frequencies of 25 and 50 MHz are about 6 and 12.5 Mb/s, respectively. About two times the speedup with 30% hardware overhead relative to the original sequential one is achieved.

UR - http://www.scopus.com/inward/record.url?scp=0035456258&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0035456258&partnerID=8YFLogxK

U2 - 10.1109/82.964994

DO - 10.1109/82.964994

M3 - Article

AN - SCOPUS:0035456258

VL - 48

SP - 813

EP - 825

JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

SN - 1057-7130

IS - 9

ER -