Abstract
In this brief, two designs of low-error fixed-width sign-magnitude parallel multipliers and two's-complement parallel multipliers for digital signal processing applications are presented. Given two n-bit inputs, the fixed-width multipliers generate n-bit (instead of 2n-bit) products with low product error, but use only about half the area and less delay when compared with a standard parallel multiplier. In them, cost-effective carry-generating circuits are designed, respectively, to make the products generated more accurately and quickly. Applying the same approach, a low-error reduced-width multiplier with output bit-width between n and 2n has also been designed. Experimental results show that the proposed fixed-width and reduced-width multipliers have lower error than all other fixed-width multipliers and are still cost-effective. Due to these properties, they are very suitable for use in many multimedia and digital signal processing applications such as digital filtering, arithmetic coding, wavelet transformation, echo cancellation, etc.
Original language | English |
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Pages (from-to) | 836-842 |
Number of pages | 7 |
Journal | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing |
Volume | 46 |
Issue number | 6 |
DOIs | |
Publication status | Published - 1999 Jun 1 |
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All Science Journal Classification (ASJC) codes
- Signal Processing
- Electrical and Electronic Engineering
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Design of low-error fixed-width multipliers for DSP applications. / Jou, Jer Min; Kuang, Shiann Rong; Chen, Ren-Der.
In: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 46, No. 6, 01.06.1999, p. 836-842.Research output: Contribution to journal › Article
TY - JOUR
T1 - Design of low-error fixed-width multipliers for DSP applications
AU - Jou, Jer Min
AU - Kuang, Shiann Rong
AU - Chen, Ren-Der
PY - 1999/6/1
Y1 - 1999/6/1
N2 - In this brief, two designs of low-error fixed-width sign-magnitude parallel multipliers and two's-complement parallel multipliers for digital signal processing applications are presented. Given two n-bit inputs, the fixed-width multipliers generate n-bit (instead of 2n-bit) products with low product error, but use only about half the area and less delay when compared with a standard parallel multiplier. In them, cost-effective carry-generating circuits are designed, respectively, to make the products generated more accurately and quickly. Applying the same approach, a low-error reduced-width multiplier with output bit-width between n and 2n has also been designed. Experimental results show that the proposed fixed-width and reduced-width multipliers have lower error than all other fixed-width multipliers and are still cost-effective. Due to these properties, they are very suitable for use in many multimedia and digital signal processing applications such as digital filtering, arithmetic coding, wavelet transformation, echo cancellation, etc.
AB - In this brief, two designs of low-error fixed-width sign-magnitude parallel multipliers and two's-complement parallel multipliers for digital signal processing applications are presented. Given two n-bit inputs, the fixed-width multipliers generate n-bit (instead of 2n-bit) products with low product error, but use only about half the area and less delay when compared with a standard parallel multiplier. In them, cost-effective carry-generating circuits are designed, respectively, to make the products generated more accurately and quickly. Applying the same approach, a low-error reduced-width multiplier with output bit-width between n and 2n has also been designed. Experimental results show that the proposed fixed-width and reduced-width multipliers have lower error than all other fixed-width multipliers and are still cost-effective. Due to these properties, they are very suitable for use in many multimedia and digital signal processing applications such as digital filtering, arithmetic coding, wavelet transformation, echo cancellation, etc.
UR - http://www.scopus.com/inward/record.url?scp=0033149483&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0033149483&partnerID=8YFLogxK
U2 - 10.1109/82.769795
DO - 10.1109/82.769795
M3 - Article
AN - SCOPUS:0033149483
VL - 46
SP - 836
EP - 842
JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
SN - 1057-7130
IS - 6
ER -