Design of low-error fixed-width multipliers for DSP applications

Jer Min Jou, Shiann Rong Kuang, Ren Der Chen

Research output: Contribution to journalArticlepeer-review

90 Citations (Scopus)

Abstract

In this brief, two designs of low-error fixed-width sign-magnitude parallel multipliers and two's-complement parallel multipliers for digital signal processing applications are presented. Given two n-bit inputs, the fixed-width multipliers generate n-bit (instead of 2n-bit) products with low product error, but use only about half the area and less delay when compared with a standard parallel multiplier. In them, cost-effective carry-generating circuits are designed, respectively, to make the products generated more accurately and quickly. Applying the same approach, a low-error reduced-width multiplier with output bit-width between n and 2n has also been designed. Experimental results show that the proposed fixed-width and reduced-width multipliers have lower error than all other fixed-width multipliers and are still cost-effective. Due to these properties, they are very suitable for use in many multimedia and digital signal processing applications such as digital filtering, arithmetic coding, wavelet transformation, echo cancellation, etc.

Original languageEnglish
Pages (from-to)836-842
Number of pages7
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume46
Issue number6
DOIs
Publication statusPublished - 1999 Jun 1

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Electrical and Electronic Engineering

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