Design of delay-locked loop for wide frequency locking range

Hsun-Hsiang Chen, Zih Hsiang Wong, Shen Li Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In order to increase the frequency locking range, a delay-locked loop (DLL) circuit with frequency to voltage converter (FVC) and phase select circuit is described. For the low power dissipation consideration, the circuit's bias current is keep at lower level. The simulation results show that the operating frequency range extend from 106 MHz ∼ 151 MHz to 54 MHz ∼ 250 MHz, and the power dissipation increases from 2.47 mW ∼ 3.33 mW to 6.7 mW ∼ 14 mW.

Original languageEnglish
Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
PublisherIEEE Computer Society
Pages302-305
Number of pages4
ISBN (Print)9781479911417
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
Duration: 2013 Nov 172013 Nov 19

Other

Other2013 International SoC Design Conference, ISOCC 2013
CountryKorea, Republic of
CityBusan
Period13-11-1713-11-19

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Chen, H-H., Wong, Z. H., & Chen, S. L. (2013). Design of delay-locked loop for wide frequency locking range. In ISOCC 2013 - 2013 International SoC Design Conference (pp. 302-305). [6864033] IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6864033