Design of an asynchronous pipelined processor

Meng-Chou Chang, Da Sen Shiau

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Asynchronous circuits have the potential advantages of low power consumption, high operating speed, low electromagnetic emission, no clock skew problem, and robustness towards variations in temperature, supply voltage and fabrication process parameters. This paper introduces the design of an asynchronous pipelined processor, called AsynRISC, which is implemented by using the asynchronous hardware description language Balsa. Since asynchronous logic adopts distributed control scheme, the traditional methods for handling hazards in synchronous processors can not be directly applied to asynchronous processors. In this paper, the methods for dealing with data hazards and control hazards in AsynRISC are discussed.

Original languageEnglish
Title of host publication2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
Pages1093-1096
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province, China
Duration: 2008 May 252008 May 27

Publication series

Name2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

Other

Other2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
CountryChina
CityXiamen, Fujian Province
Period08-05-2508-05-27

Fingerprint

Hazards
Computer hardware description languages
Clocks
Electric power utilization
Fabrication
Networks (circuits)
Electric potential
Temperature

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Chang, M-C., & Shiau, D. S. (2008). Design of an asynchronous pipelined processor. In 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008 (pp. 1093-1096). [4657958] (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008). https://doi.org/10.1109/ICCCAS.2008.4657958
Chang, Meng-Chou ; Shiau, Da Sen. / Design of an asynchronous pipelined processor. 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. pp. 1093-1096 (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008).
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Chang, M-C & Shiau, DS 2008, Design of an asynchronous pipelined processor. in 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008., 4657958, 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008, pp. 1093-1096, 2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008, Xiamen, Fujian Province, China, 08-05-25. https://doi.org/10.1109/ICCCAS.2008.4657958

Design of an asynchronous pipelined processor. / Chang, Meng-Chou; Shiau, Da Sen.

2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 1093-1096 4657958 (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chang M-C, Shiau DS. Design of an asynchronous pipelined processor. In 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 1093-1096. 4657958. (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008). https://doi.org/10.1109/ICCCAS.2008.4657958