Design of a transparent pipeline based on synchronous elastic circuits

Ren-Der Chen, Sheng Hung Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This chapter presents a transparent pipeline architecture based on the synchronous elastic circuits. Compared with a traditional synchronous pipeline, a transparent pipeline can reduce dynamic clock power dissipation by reducing the amount of clock pulses required for data latching. Moreover, with the help of the synchronous elastic properties, our design can also provide tolerance to variations in computation and communication delays. The proposed architecture has been implemented by the Verilog HDL and synthesized with Altera Quartus II. The experimental results performed on a five-stage pipeline have also shown the power efficiency of our architecture.

Original languageEnglish
Title of host publicationIntelligent Technologies and Engineering Systems
Pages625-631
Number of pages7
DOIs
Publication statusPublished - 2013 Aug 8
Event2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012 - Changhua, Taiwan
Duration: 2012 Dec 132012 Dec 15

Publication series

NameLecture Notes in Electrical Engineering
Volume234 LNEE
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

Other

Other2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012
CountryTaiwan
CityChanghua
Period12-12-1312-12-15

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All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering

Cite this

Chen, R-D., & Chang, S. H. (2013). Design of a transparent pipeline based on synchronous elastic circuits. In Intelligent Technologies and Engineering Systems (pp. 625-631). (Lecture Notes in Electrical Engineering; Vol. 234 LNEE). https://doi.org/10.1007/978-1-4614-6747-2_73