Abstract
This chapter presents a transparent pipeline architecture based on the synchronous elastic circuits. Compared with a traditional synchronous pipeline, a transparent pipeline can reduce dynamic clock power dissipation by reducing the amount of clock pulses required for data latching. Moreover, with the help of the synchronous elastic properties, our design can also provide tolerance to variations in computation and communication delays. The proposed architecture has been implemented by the Verilog HDL and synthesized with Altera Quartus II. The experimental results performed on a five-stage pipeline have also shown the power efficiency of our architecture.
| Original language | English |
|---|---|
| Title of host publication | Intelligent Technologies and Engineering Systems |
| Pages | 625-631 |
| Number of pages | 7 |
| DOIs | |
| Publication status | Published - 2013 Aug 8 |
| Event | 2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012 - Changhua, Taiwan Duration: 2012 Dec 13 → 2012 Dec 15 |
Publication series
| Name | Lecture Notes in Electrical Engineering |
|---|---|
| Volume | 234 LNEE |
| ISSN (Print) | 1876-1100 |
| ISSN (Electronic) | 1876-1119 |
Other
| Other | 2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012 |
|---|---|
| Country | Taiwan |
| City | Changhua |
| Period | 12-12-13 → 12-12-15 |
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All Science Journal Classification (ASJC) codes
- Industrial and Manufacturing Engineering
Cite this
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Design of a transparent pipeline based on synchronous elastic circuits. / Chen, Ren-Der; Chang, Sheng Hung.
Intelligent Technologies and Engineering Systems. 2013. p. 625-631 (Lecture Notes in Electrical Engineering; Vol. 234 LNEE).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Design of a transparent pipeline based on synchronous elastic circuits
AU - Chen, Ren-Der
AU - Chang, Sheng Hung
PY - 2013/8/8
Y1 - 2013/8/8
N2 - This chapter presents a transparent pipeline architecture based on the synchronous elastic circuits. Compared with a traditional synchronous pipeline, a transparent pipeline can reduce dynamic clock power dissipation by reducing the amount of clock pulses required for data latching. Moreover, with the help of the synchronous elastic properties, our design can also provide tolerance to variations in computation and communication delays. The proposed architecture has been implemented by the Verilog HDL and synthesized with Altera Quartus II. The experimental results performed on a five-stage pipeline have also shown the power efficiency of our architecture.
AB - This chapter presents a transparent pipeline architecture based on the synchronous elastic circuits. Compared with a traditional synchronous pipeline, a transparent pipeline can reduce dynamic clock power dissipation by reducing the amount of clock pulses required for data latching. Moreover, with the help of the synchronous elastic properties, our design can also provide tolerance to variations in computation and communication delays. The proposed architecture has been implemented by the Verilog HDL and synthesized with Altera Quartus II. The experimental results performed on a five-stage pipeline have also shown the power efficiency of our architecture.
UR - http://www.scopus.com/inward/record.url?scp=84881037675&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84881037675&partnerID=8YFLogxK
U2 - 10.1007/978-1-4614-6747-2_73
DO - 10.1007/978-1-4614-6747-2_73
M3 - Conference contribution
AN - SCOPUS:84881037675
SN - 9781461467465
T3 - Lecture Notes in Electrical Engineering
SP - 625
EP - 631
BT - Intelligent Technologies and Engineering Systems
ER -