Abstract
This chapter implements an 8 x 8 multiplier based on the transparent pipeline architecture. A transparent pipeline can lower the power consumption by reducing the number of clock pulses required for data latch controlling. The efficiency of power saving is evaluated here by applying the multiplier to the multiplication of two sparse matrices. It can be seen from the experimental results that, when compared with the traditional synchronous multiplier using flip-flops as storage elements, the improvement in power consumption is obvious only when the sparsity of the matrix reaches a certain amount.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 |
| Editors | Jengnan Juang |
| Publisher | Springer Verlag |
| Pages | 485-491 |
| Number of pages | 7 |
| ISBN (Print) | 9783319173139 |
| DOIs | |
| Publication status | Published - 2016 Jan 1 |
| Event | 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 - Kaohsiung, Taiwan Duration: 2014 Dec 19 → 2014 Dec 21 |
Publication series
| Name | Lecture Notes in Electrical Engineering |
|---|---|
| Volume | 345 |
| ISSN (Print) | 1876-1100 |
| ISSN (Electronic) | 1876-1119 |
Other
| Other | 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 |
|---|---|
| Country | Taiwan |
| City | Kaohsiung |
| Period | 14-12-19 → 14-12-21 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Industrial and Manufacturing Engineering
Cite this
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Design of a transparent pipeline-based multiplier. / Chen, Ren-Der; Kuo, Xiang Chih.
Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014. ed. / Jengnan Juang. Springer Verlag, 2016. p. 485-491 (Lecture Notes in Electrical Engineering; Vol. 345).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Design of a transparent pipeline-based multiplier
AU - Chen, Ren-Der
AU - Kuo, Xiang Chih
PY - 2016/1/1
Y1 - 2016/1/1
N2 - This chapter implements an 8 x 8 multiplier based on the transparent pipeline architecture. A transparent pipeline can lower the power consumption by reducing the number of clock pulses required for data latch controlling. The efficiency of power saving is evaluated here by applying the multiplier to the multiplication of two sparse matrices. It can be seen from the experimental results that, when compared with the traditional synchronous multiplier using flip-flops as storage elements, the improvement in power consumption is obvious only when the sparsity of the matrix reaches a certain amount.
AB - This chapter implements an 8 x 8 multiplier based on the transparent pipeline architecture. A transparent pipeline can lower the power consumption by reducing the number of clock pulses required for data latch controlling. The efficiency of power saving is evaluated here by applying the multiplier to the multiplication of two sparse matrices. It can be seen from the experimental results that, when compared with the traditional synchronous multiplier using flip-flops as storage elements, the improvement in power consumption is obvious only when the sparsity of the matrix reaches a certain amount.
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U2 - 10.1007/978-3-319-17314-6_62
DO - 10.1007/978-3-319-17314-6_62
M3 - Conference contribution
AN - SCOPUS:84951918795
SN - 9783319173139
T3 - Lecture Notes in Electrical Engineering
SP - 485
EP - 491
BT - Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014
A2 - Juang, Jengnan
PB - Springer Verlag
ER -