Design of a transparent pipeline-based multiplier

Ren-Der Chen, Xiang Chih Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This chapter implements an 8 x 8 multiplier based on the transparent pipeline architecture. A transparent pipeline can lower the power consumption by reducing the number of clock pulses required for data latch controlling. The efficiency of power saving is evaluated here by applying the multiplier to the multiplication of two sparse matrices. It can be seen from the experimental results that, when compared with the traditional synchronous multiplier using flip-flops as storage elements, the improvement in power consumption is obvious only when the sparsity of the matrix reaches a certain amount.

Original languageEnglish
Title of host publicationProceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014
EditorsJengnan Juang
PublisherSpringer Verlag
Pages485-491
Number of pages7
ISBN (Print)9783319173139
DOIs
Publication statusPublished - 2016 Jan 1
Event3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 - Kaohsiung, Taiwan
Duration: 2014 Dec 192014 Dec 21

Publication series

NameLecture Notes in Electrical Engineering
Volume345
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

Other

Other3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014
CountryTaiwan
CityKaohsiung
Period14-12-1914-12-21

Fingerprint

Electric power utilization
Pipelines
Flip flop circuits
Clocks

All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering

Cite this

Chen, R-D., & Kuo, X. C. (2016). Design of a transparent pipeline-based multiplier. In J. Juang (Ed.), Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 (pp. 485-491). (Lecture Notes in Electrical Engineering; Vol. 345). Springer Verlag. https://doi.org/10.1007/978-3-319-17314-6_62
Chen, Ren-Der ; Kuo, Xiang Chih. / Design of a transparent pipeline-based multiplier. Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014. editor / Jengnan Juang. Springer Verlag, 2016. pp. 485-491 (Lecture Notes in Electrical Engineering).
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Chen, R-D & Kuo, XC 2016, Design of a transparent pipeline-based multiplier. in J Juang (ed.), Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014. Lecture Notes in Electrical Engineering, vol. 345, Springer Verlag, pp. 485-491, 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014, Kaohsiung, Taiwan, 14-12-19. https://doi.org/10.1007/978-3-319-17314-6_62

Design of a transparent pipeline-based multiplier. / Chen, Ren-Der; Kuo, Xiang Chih.

Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014. ed. / Jengnan Juang. Springer Verlag, 2016. p. 485-491 (Lecture Notes in Electrical Engineering; Vol. 345).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chen R-D, Kuo XC. Design of a transparent pipeline-based multiplier. In Juang J, editor, Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014. Springer Verlag. 2016. p. 485-491. (Lecture Notes in Electrical Engineering). https://doi.org/10.1007/978-3-319-17314-6_62