@inproceedings{f63f4c0edecf442a86a6d7548c8fe903,
title = "Design of a transparent pipeline-based multiplier",
abstract = "This chapter implements an 8 x 8 multiplier based on the transparent pipeline architecture. A transparent pipeline can lower the power consumption by reducing the number of clock pulses required for data latch controlling. The efficiency of power saving is evaluated here by applying the multiplier to the multiplication of two sparse matrices. It can be seen from the experimental results that, when compared with the traditional synchronous multiplier using flip-flops as storage elements, the improvement in power consumption is obvious only when the sparsity of the matrix reaches a certain amount.",
author = "Ren-Der Chen and Kuo, {Xiang Chih}",
year = "2016",
month = jan,
day = "1",
doi = "10.1007/978-3-319-17314-6_62",
language = "English",
isbn = "9783319173139",
series = "Lecture Notes in Electrical Engineering",
publisher = "Springer Verlag",
pages = "485--491",
editor = "Jengnan Juang",
booktitle = "Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014",
address = "Germany",
note = "3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 ; Conference date: 19-12-2014 Through 21-12-2014",
}