Design of a transparent pipeline-based multiplier

Ren-Der Chen; Xiang Chih Kuo

doi:10.1007/978-3-319-17314-6_62

Design of a transparent pipeline-based multiplier

Ren-Der Chen, Xiang Chih Kuo

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This chapter implements an 8 x 8 multiplier based on the transparent pipeline architecture. A transparent pipeline can lower the power consumption by reducing the number of clock pulses required for data latch controlling. The efficiency of power saving is evaluated here by applying the multiplier to the multiplication of two sparse matrices. It can be seen from the experimental results that, when compared with the traditional synchronous multiplier using flip-flops as storage elements, the improvement in power consumption is obvious only when the sparsity of the matrix reaches a certain amount.

Original language	English
Title of host publication	Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014
Editors	Jengnan Juang
Publisher	Springer Verlag
Pages	485-491
Number of pages	7
ISBN (Print)	9783319173139
DOIs	https://doi.org/10.1007/978-3-319-17314-6_62
Publication status	Published - 2016 Jan 1
Event	3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 - Kaohsiung, Taiwan Duration: 2014 Dec 19 → 2014 Dec 21

Publication series

Name	Lecture Notes in Electrical Engineering
Volume	345
ISSN (Print)	1876-1100
ISSN (Electronic)	1876-1119

Other

Other	3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014
Country	Taiwan
City	Kaohsiung
Period	14-12-19 → 14-12-21

All Science Journal Classification (ASJC) codes

Industrial and Manufacturing Engineering

Access to Document

10.1007/978-3-319-17314-6_62

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Chen, R-D., & Kuo, X. C. (2016). Design of a transparent pipeline-based multiplier. In J. Juang (Ed.), Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 (pp. 485-491). (Lecture Notes in Electrical Engineering; Vol. 345). Springer Verlag. https://doi.org/10.1007/978-3-319-17314-6_62

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Chen, R-D & Kuo, XC 2016, Design of a transparent pipeline-based multiplier. in J Juang (ed.), Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014. Lecture Notes in Electrical Engineering, vol. 345, Springer Verlag, pp. 485-491, 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014, Kaohsiung, Taiwan, 14-12-19. https://doi.org/10.1007/978-3-319-17314-6_62

Design of a transparent pipeline-based multiplier. / Chen, Ren-Der; Kuo, Xiang Chih.

Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014. ed. / Jengnan Juang. Springer Verlag, 2016. p. 485-491 (Lecture Notes in Electrical Engineering; Vol. 345).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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