Design of a dynamic pipelined architecture for fuzzy color correction

Jer Min Jou, Shiann Rong Kuang, Yeu Horng Shiau, Ren-Der Chen

Research output: Contribution to journalArticle

Abstract

Color correction, which nonlinearly converts the color coordinates of an input device such as the scanner and digital camera into that of an output device such as the color laser printer, is important for multimedia applications. In this brief, we present a novel dynamic pipelined VLSI architecture for the fuzzy color correction algorithm (FCC) proposed by Jan et al. to meet the speed requirement of time-critical applications. To promote the performance, the presented architecture is dynamically pipelined with unfixed or run-time determined latencies (or data initiation intervals) and the speculation technique is also applied, then the problems of arduous pipelining, due to the variant execution time of each iteration and slower executing of FCC are solved efficiently. As for data path design, a systematic design methodology of high-level synthesis is used. As a result, a significant (about 2 times) speedup of the dynamic pipelined architecture with a slight hardware overhead relative to the sequential one has been achieved.

Original languageEnglish
Pages (from-to)924-929
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume10
Issue number6
DOIs
Publication statusPublished - 2002 Dec 1

Fingerprint

Color
Digital cameras
Hardware
Lasers

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

@article{700a567264184a48b0f83685721a8e2d,
title = "Design of a dynamic pipelined architecture for fuzzy color correction",
abstract = "Color correction, which nonlinearly converts the color coordinates of an input device such as the scanner and digital camera into that of an output device such as the color laser printer, is important for multimedia applications. In this brief, we present a novel dynamic pipelined VLSI architecture for the fuzzy color correction algorithm (FCC) proposed by Jan et al. to meet the speed requirement of time-critical applications. To promote the performance, the presented architecture is dynamically pipelined with unfixed or run-time determined latencies (or data initiation intervals) and the speculation technique is also applied, then the problems of arduous pipelining, due to the variant execution time of each iteration and slower executing of FCC are solved efficiently. As for data path design, a systematic design methodology of high-level synthesis is used. As a result, a significant (about 2 times) speedup of the dynamic pipelined architecture with a slight hardware overhead relative to the sequential one has been achieved.",
author = "Jou, {Jer Min} and Kuang, {Shiann Rong} and Shiau, {Yeu Horng} and Ren-Der Chen",
year = "2002",
month = "12",
day = "1",
doi = "10.1109/TVLSI.2002.808458",
language = "English",
volume = "10",
pages = "924--929",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "6",

}

Design of a dynamic pipelined architecture for fuzzy color correction. / Jou, Jer Min; Kuang, Shiann Rong; Shiau, Yeu Horng; Chen, Ren-Der.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 6, 01.12.2002, p. 924-929.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Design of a dynamic pipelined architecture for fuzzy color correction

AU - Jou, Jer Min

AU - Kuang, Shiann Rong

AU - Shiau, Yeu Horng

AU - Chen, Ren-Der

PY - 2002/12/1

Y1 - 2002/12/1

N2 - Color correction, which nonlinearly converts the color coordinates of an input device such as the scanner and digital camera into that of an output device such as the color laser printer, is important for multimedia applications. In this brief, we present a novel dynamic pipelined VLSI architecture for the fuzzy color correction algorithm (FCC) proposed by Jan et al. to meet the speed requirement of time-critical applications. To promote the performance, the presented architecture is dynamically pipelined with unfixed or run-time determined latencies (or data initiation intervals) and the speculation technique is also applied, then the problems of arduous pipelining, due to the variant execution time of each iteration and slower executing of FCC are solved efficiently. As for data path design, a systematic design methodology of high-level synthesis is used. As a result, a significant (about 2 times) speedup of the dynamic pipelined architecture with a slight hardware overhead relative to the sequential one has been achieved.

AB - Color correction, which nonlinearly converts the color coordinates of an input device such as the scanner and digital camera into that of an output device such as the color laser printer, is important for multimedia applications. In this brief, we present a novel dynamic pipelined VLSI architecture for the fuzzy color correction algorithm (FCC) proposed by Jan et al. to meet the speed requirement of time-critical applications. To promote the performance, the presented architecture is dynamically pipelined with unfixed or run-time determined latencies (or data initiation intervals) and the speculation technique is also applied, then the problems of arduous pipelining, due to the variant execution time of each iteration and slower executing of FCC are solved efficiently. As for data path design, a systematic design methodology of high-level synthesis is used. As a result, a significant (about 2 times) speedup of the dynamic pipelined architecture with a slight hardware overhead relative to the sequential one has been achieved.

UR - http://www.scopus.com/inward/record.url?scp=0036999789&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036999789&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2002.808458

DO - 10.1109/TVLSI.2002.808458

M3 - Article

AN - SCOPUS:0036999789

VL - 10

SP - 924

EP - 929

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 6

ER -