Congruence synchronous mirror delay

Tsung Chu Huang, Gau Bin Chang, Ng Li

Research output: Contribution to journalConference articlepeer-review


Digital synchronous mirror delaylines can lock in only two cycles and make burst and sleep modes feasible for high-speed and low-power applications. Conventional digital synchronous mirror delay usually spends at least one delay line with a length comparable to the resolution. The area overhead becomes an issue in multiple-module circuits. The objective of this paper is thus to reduce the area overhead by folding the delayline. Simple corollaries from the congruence theorem are derived for function proves. Experimental results show that the proposed design can save more than 75% of area overhead for fixed skew compensation of hundreds of stages under acceptable phase errors.

Original languageEnglish
Article number4253105
Pages (from-to)2184-2187
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 2007
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: 2007 May 272007 May 30

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Congruence synchronous mirror delay'. Together they form a unique fingerprint.

Cite this