Comparison of two data hazard handling schemes for asynchronous pipelined processors

Meng-Chou Chang, Da Sen Shiau

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Since asynchronous logic adopts a distributed control scheme, the traditional methods for handling hazards in synchronous processors cannot be directly applied to asynchronous processors. Recently, the data hazard detection table (DHDT) scheme has been regarded as an effective method for handling data hazards in asynchronous processors. In this paper, two asynchronous data hazard handling schemes, the DHDT scheme and the proposed destination register chain (DRC) scheme, are compared in terms of performance and hardware complexity. In order to evaluate these two data hazard handling schemes, we have used the Balsa asynchronous synthesis system to implement two asynchronous pipelined processors, AsynRISC-DHDT and AsynRISC-DRC, which employ DHDT and DRC, respectively, to deal with data hazards. Experimental results show that AsynRISC-DRC can achieve a 13% reduction in hardware area cost and a performance gain of 22.1% compared with AsynRISC-DHDT.

Original languageEnglish
Title of host publicationProceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
Pages36-40
Number of pages5
DOIs
Publication statusPublished - 2010 Nov 1
Event2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010 - Chengdu, China
Duration: 2010 Jul 92010 Jul 11

Publication series

NameProceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
Volume4

Other

Other2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
CountryChina
CityChengdu
Period10-07-0910-07-11

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All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Electrical and Electronic Engineering

Cite this

Chang, M-C., & Shiau, D. S. (2010). Comparison of two data hazard handling schemes for asynchronous pipelined processors. In Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010 (pp. 36-40). [5563539] (Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010; Vol. 4). https://doi.org/10.1109/ICCSIT.2010.5563539