Comparative design of floating-point arithmetic units using the Balsa synthesis system

Ren-Der Chen, Yu Cheng Chou, Wan Chen Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, the asynchronous floating-point arithmetic units consisting of adders/subtractors and multipliers are designed and compared based on the Balsa synthesis system. For the critical mantissa multiplication in the multiplier, the modified Booth algorithm (radix 2, 4, and 8) is adopted. A pipelined design of the multiplier is also presented to increase performance. Since the Balsa language is compiled using syntax-directed translation, for the two different if statements and one case statement supported by Balsa, three different description styles have been made for each design. It can be seen from the experimental results how the style affects the area cost and simulation time of the resulting circuit. This gives us a guide to choose appropriate control statements for designing Balsa-based asynchronous circuits.

Original languageEnglish
Title of host publication2011 International Symposium on Integrated Circuits, ISIC 2011
Pages172-175
Number of pages4
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore, Singapore
Duration: 2011 Dec 122011 Dec 14

Publication series

Name2011 International Symposium on Integrated Circuits, ISIC 2011

Other

Other2011 International Symposium on Integrated Circuits, ISIC 2011
CountrySingapore
CitySingaporeSingapore
Period11-12-1211-12-14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Comparative design of floating-point arithmetic units using the Balsa synthesis system'. Together they form a unique fingerprint.

Cite this