TY - GEN
T1 - Comparative design of floating-point arithmetic units using the Balsa synthesis system
AU - Chen, Ren-Der
AU - Chou, Yu Cheng
AU - Liu, Wan Chen
PY - 2011/12/1
Y1 - 2011/12/1
N2 - In this paper, the asynchronous floating-point arithmetic units consisting of adders/subtractors and multipliers are designed and compared based on the Balsa synthesis system. For the critical mantissa multiplication in the multiplier, the modified Booth algorithm (radix 2, 4, and 8) is adopted. A pipelined design of the multiplier is also presented to increase performance. Since the Balsa language is compiled using syntax-directed translation, for the two different if statements and one case statement supported by Balsa, three different description styles have been made for each design. It can be seen from the experimental results how the style affects the area cost and simulation time of the resulting circuit. This gives us a guide to choose appropriate control statements for designing Balsa-based asynchronous circuits.
AB - In this paper, the asynchronous floating-point arithmetic units consisting of adders/subtractors and multipliers are designed and compared based on the Balsa synthesis system. For the critical mantissa multiplication in the multiplier, the modified Booth algorithm (radix 2, 4, and 8) is adopted. A pipelined design of the multiplier is also presented to increase performance. Since the Balsa language is compiled using syntax-directed translation, for the two different if statements and one case statement supported by Balsa, three different description styles have been made for each design. It can be seen from the experimental results how the style affects the area cost and simulation time of the resulting circuit. This gives us a guide to choose appropriate control statements for designing Balsa-based asynchronous circuits.
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U2 - 10.1109/ISICir.2011.6131905
DO - 10.1109/ISICir.2011.6131905
M3 - Conference contribution
AN - SCOPUS:84863065645
SN - 9781612848648
T3 - 2011 International Symposium on Integrated Circuits, ISIC 2011
SP - 172
EP - 175
BT - 2011 International Symposium on Integrated Circuits, ISIC 2011
T2 - 2011 International Symposium on Integrated Circuits, ISIC 2011
Y2 - 12 December 2011 through 14 December 2011
ER -