Abstract
In this paper, the asynchronous floating-point arithmetic units consisting of adders/subtractors and multipliers are designed and compared based on the Balsa synthesis system. For the critical mantissa multiplication in the multiplier, the modified Booth algorithm (radix 2, 4, and 8) is adopted. A pipelined design of the multiplier is also presented to increase performance. Since the Balsa language is compiled using syntax-directed translation, for the two different if statements and one case statement supported by Balsa, three different description styles have been made for each design. It can be seen from the experimental results how the style affects the area cost and simulation time of the resulting circuit. This gives us a guide to choose appropriate control statements for designing Balsa-based asynchronous circuits.
| Original language | English |
|---|---|
| Title of host publication | 2011 International Symposium on Integrated Circuits, ISIC 2011 |
| Pages | 172-175 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2011 Dec 1 |
| Event | 2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore, Singapore Duration: 2011 Dec 12 → 2011 Dec 14 |
Publication series
| Name | 2011 International Symposium on Integrated Circuits, ISIC 2011 |
|---|
Other
| Other | 2011 International Symposium on Integrated Circuits, ISIC 2011 |
|---|---|
| Country | Singapore |
| City | SingaporeSingapore |
| Period | 11-12-12 → 11-12-14 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
}
Comparative design of floating-point arithmetic units using the Balsa synthesis system. / Chen, Ren-Der; Chou, Yu Cheng; Liu, Wan Chen.
2011 International Symposium on Integrated Circuits, ISIC 2011. 2011. p. 172-175 6131905 (2011 International Symposium on Integrated Circuits, ISIC 2011).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Comparative design of floating-point arithmetic units using the Balsa synthesis system
AU - Chen, Ren-Der
AU - Chou, Yu Cheng
AU - Liu, Wan Chen
PY - 2011/12/1
Y1 - 2011/12/1
N2 - In this paper, the asynchronous floating-point arithmetic units consisting of adders/subtractors and multipliers are designed and compared based on the Balsa synthesis system. For the critical mantissa multiplication in the multiplier, the modified Booth algorithm (radix 2, 4, and 8) is adopted. A pipelined design of the multiplier is also presented to increase performance. Since the Balsa language is compiled using syntax-directed translation, for the two different if statements and one case statement supported by Balsa, three different description styles have been made for each design. It can be seen from the experimental results how the style affects the area cost and simulation time of the resulting circuit. This gives us a guide to choose appropriate control statements for designing Balsa-based asynchronous circuits.
AB - In this paper, the asynchronous floating-point arithmetic units consisting of adders/subtractors and multipliers are designed and compared based on the Balsa synthesis system. For the critical mantissa multiplication in the multiplier, the modified Booth algorithm (radix 2, 4, and 8) is adopted. A pipelined design of the multiplier is also presented to increase performance. Since the Balsa language is compiled using syntax-directed translation, for the two different if statements and one case statement supported by Balsa, three different description styles have been made for each design. It can be seen from the experimental results how the style affects the area cost and simulation time of the resulting circuit. This gives us a guide to choose appropriate control statements for designing Balsa-based asynchronous circuits.
UR - http://www.scopus.com/inward/record.url?scp=84863065645&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84863065645&partnerID=8YFLogxK
U2 - 10.1109/ISICir.2011.6131905
DO - 10.1109/ISICir.2011.6131905
M3 - Conference contribution
AN - SCOPUS:84863065645
SN - 9781612848648
T3 - 2011 International Symposium on Integrated Circuits, ISIC 2011
SP - 172
EP - 175
BT - 2011 International Symposium on Integrated Circuits, ISIC 2011
ER -