Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs

Tsung-Yi Wu; Tzi Wei Kao; Shi Yi Huang; Tai Lun Li; How Rern Lin

doi:10.1109/ASPDAC.2010.5419842

Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs

Tsung-Yi Wu, Tzi Wei Kao, Shi Yi Huang, Tai Lun Li, How Rern Lin

Department of Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In a typical synchronous SoC design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.

Original language	English
Title of host publication	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Pages	444-449
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2010.5419842
Publication status	Published - 2010 Apr 28
Event	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan Duration: 2010 Jan 18 → 2010 Jan 21

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Country	Taiwan
City	Taipei
Period	10-01-18 → 10-01-21

All Science Journal Classification (ASJC) codes

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2010.5419842

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Cite this

Wu, T-Y., Kao, T. W., Huang, S. Y., Li, T. L., & Lin, H. R. (2010). Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. In 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 (pp. 444-449). [5419842] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2010.5419842

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abstract = "In a typical synchronous SoC design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.",

author = "Tsung-Yi Wu and Kao, {Tzi Wei} and Huang, {Shi Yi} and Li, {Tai Lun} and Lin, {How Rern}",

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Wu, T-Y, Kao, TW, Huang, SY, Li, TL & Lin, HR 2010, Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. in 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010., 5419842, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 444-449, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, 10-01-18. https://doi.org/10.1109/ASPDAC.2010.5419842

Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. / Wu, Tsung-Yi; Kao, Tzi Wei; Huang, Shi Yi; Li, Tai Lun; Lin, How Rern.

2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. 2010. p. 444-449 5419842 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Wu T-Y, Kao TW, Huang SY, Li TL, Lin HR. Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. In 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. 2010. p. 444-449. 5419842. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2010.5419842