TY - GEN
T1 - Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs
AU - Wu, Tsung-Yi
AU - Kao, Tzi Wei
AU - Huang, Shi Yi
AU - Li, Tai Lun
AU - Lin, How Rern
PY - 2010/4/28
Y1 - 2010/4/28
N2 - In a typical synchronous SoC design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.
AB - In a typical synchronous SoC design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.
UR - http://www.scopus.com/inward/record.url?scp=77951217014&partnerID=8YFLogxK
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U2 - 10.1109/ASPDAC.2010.5419842
DO - 10.1109/ASPDAC.2010.5419842
M3 - Conference contribution
AN - SCOPUS:77951217014
SN - 9781424457656
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 444
EP - 449
BT - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
T2 - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Y2 - 18 January 2010 through 21 January 2010
ER -