Combination of automatic test pattern generation and built-in intermediate voltage sensing for detecting CMOS bridging faults

Kuen Jong Lee, Jing Jou Tang, Tsung Chu Huang, Cheng Liang Tsai

Research output: Contribution to journalConference article

2 Citations (Scopus)


This paper presents the BIFEST, an ATPG system that combines the conventional ATPG process and the built-in intemediate voltage test technique to deal with CMOS bridging faults. A PODEM-like, PPSFP-based ATPG process that can effectively and efficiently model the bridging fault effects is developed to process those faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits called built-in intermediate voltage sensors. By this methodology almost the same fault coverage as that employing IDDQ testing can be achieved with only logic monitoring required.

Original languageEnglish
Pages (from-to)100-105
Number of pages6
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 1996 Dec 1
EventProceedings of the 1996 5th Asian Test Symposium, ATS'96 - Hsinchu, Taiwan
Duration: 1996 Nov 201996 Nov 22


All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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