CMOS driver for heavy-load flat-panel scan-line circuit based on complementary dual-bootstrap

Shu Chung Yi; Zhi Ming Lin; Po Yo Kuo; Hsin Chi Lai

doi:10.1587/transele.E96.C.1399

CMOS driver for heavy-load flat-panel scan-line circuit based on complementary dual-bootstrap

Shu Chung Yi, Zhi Ming Lin, Po Yo Kuo, Hsin Chi Lai

Department of Computer Science and Information Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

This paper, presents a high-speed full swing driver for a heavy-load flat-panel scan-line circuit. The high driving capability is achieved using the proposed Complementary Dual-Bootstrap (CDUB) technique. The scan-line CDUB driver was fabricated in a 0.35-?m CMOS technology. The measured results, under the flat-panel scan-line load model, indicate that the delay time is within 2.8 ?s and the average power is 0.74mW for a 5V supply voltage.

Original language	English
Pages (from-to)	1399-1403
Number of pages	5
Journal	IEICE Transactions on Electronics
Volume	E96-C
Issue number	11
DOIs	https://doi.org/10.1587/transele.E96.C.1399
Publication status	Published - 2013 Nov

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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@article{9cd79d74d4f146a1a0cf11a16b0345f2,

title = "CMOS driver for heavy-load flat-panel scan-line circuit based on complementary dual-bootstrap",

abstract = "This paper, presents a high-speed full swing driver for a heavy-load flat-panel scan-line circuit. The high driving capability is achieved using the proposed Complementary Dual-Bootstrap (CDUB) technique. The scan-line CDUB driver was fabricated in a 0.35-?m CMOS technology. The measured results, under the flat-panel scan-line load model, indicate that the delay time is within 2.8 ?s and the average power is 0.74mW for a 5V supply voltage.",

author = "Yi, {Shu Chung} and Lin, {Zhi Ming} and Kuo, {Po Yo} and Lai, {Hsin Chi}",

year = "2013",

month = nov,

doi = "10.1587/transele.E96.C.1399",

language = "English",

volume = "E96-C",

pages = "1399--1403",

journal = "IEICE Transactions on Electronics",

issn = "0916-8524",

publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",

number = "11",

}

TY - JOUR

T1 - CMOS driver for heavy-load flat-panel scan-line circuit based on complementary dual-bootstrap

AU - Yi, Shu Chung

AU - Lin, Zhi Ming

AU - Kuo, Po Yo

AU - Lai, Hsin Chi

PY - 2013/11

Y1 - 2013/11

N2 - This paper, presents a high-speed full swing driver for a heavy-load flat-panel scan-line circuit. The high driving capability is achieved using the proposed Complementary Dual-Bootstrap (CDUB) technique. The scan-line CDUB driver was fabricated in a 0.35-?m CMOS technology. The measured results, under the flat-panel scan-line load model, indicate that the delay time is within 2.8 ?s and the average power is 0.74mW for a 5V supply voltage.

AB - This paper, presents a high-speed full swing driver for a heavy-load flat-panel scan-line circuit. The high driving capability is achieved using the proposed Complementary Dual-Bootstrap (CDUB) technique. The scan-line CDUB driver was fabricated in a 0.35-?m CMOS technology. The measured results, under the flat-panel scan-line load model, indicate that the delay time is within 2.8 ?s and the average power is 0.74mW for a 5V supply voltage.

UR - http://www.scopus.com/inward/record.url?scp=84888579768&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84888579768&partnerID=8YFLogxK

U2 - 10.1587/transele.E96.C.1399

DO - 10.1587/transele.E96.C.1399

M3 - Article

AN - SCOPUS:84888579768

VL - E96-C

SP - 1399

EP - 1403

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 11

ER -