Abstract
This paper, presents a high-speed full swing driver for a heavy-load flat-panel scan-line circuit. The high driving capability is achieved using the proposed Complementary Dual-Bootstrap (CDUB) technique. The scan-line CDUB driver was fabricated in a 0.35-?m CMOS technology. The measured results, under the flat-panel scan-line load model, indicate that the delay time is within 2.8 ?s and the average power is 0.74mW for a 5V supply voltage.
| Original language | English |
|---|---|
| Pages (from-to) | 1399-1403 |
| Number of pages | 5 |
| Journal | IEICE Transactions on Electronics |
| Volume | E96-C |
| Issue number | 11 |
| DOIs | |
| Publication status | Published - 2013 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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CMOS driver for heavy-load flat-panel scan-line circuit based on complementary dual-bootstrap. / Yi, Shu-chung; Lin, Zhi-Ming; Kuo, Po Yo; Lai, Hsin Chi.
In: IEICE Transactions on Electronics, Vol. E96-C, No. 11, 01.01.2013, p. 1399-1403.Research output: Contribution to journal › Article
TY - JOUR
T1 - CMOS driver for heavy-load flat-panel scan-line circuit based on complementary dual-bootstrap
AU - Yi, Shu-chung
AU - Lin, Zhi-Ming
AU - Kuo, Po Yo
AU - Lai, Hsin Chi
PY - 2013/1/1
Y1 - 2013/1/1
N2 - This paper, presents a high-speed full swing driver for a heavy-load flat-panel scan-line circuit. The high driving capability is achieved using the proposed Complementary Dual-Bootstrap (CDUB) technique. The scan-line CDUB driver was fabricated in a 0.35-?m CMOS technology. The measured results, under the flat-panel scan-line load model, indicate that the delay time is within 2.8 ?s and the average power is 0.74mW for a 5V supply voltage.
AB - This paper, presents a high-speed full swing driver for a heavy-load flat-panel scan-line circuit. The high driving capability is achieved using the proposed Complementary Dual-Bootstrap (CDUB) technique. The scan-line CDUB driver was fabricated in a 0.35-?m CMOS technology. The measured results, under the flat-panel scan-line load model, indicate that the delay time is within 2.8 ?s and the average power is 0.74mW for a 5V supply voltage.
UR - http://www.scopus.com/inward/record.url?scp=84888579768&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84888579768&partnerID=8YFLogxK
U2 - 10.1587/transele.E96.C.1399
DO - 10.1587/transele.E96.C.1399
M3 - Article
AN - SCOPUS:84888579768
VL - E96-C
SP - 1399
EP - 1403
JO - IEICE Transactions on Electronics
JF - IEICE Transactions on Electronics
SN - 0916-8524
IS - 11
ER -