Cluster-error correction for through-silicon vias in 3D ics

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Abstract

The two-dimensional parity check is the optimum single-error-correction code in terms of speed. In this reported work it is employed to develop two sliding schemes for through-silicon-via cluster error correction in three-dimensional ICs. For k bits of source data, the onedimensional sliding scheme can correct a single cluster error up to about √k bits and more extra discrete errors can be corrected by the two-dimensional sliding scheme. Experiments show that for several hundreds of through-silicon vias (TSVs), two trees of 3-level 2-input exclusive-OR (XOR) gates are almost optimised to encode and decode each interconnect, and the time penalty can be controlled within about 1 ns.

Original languageEnglish
Pages (from-to)289-290
Number of pages2
JournalElectronics Letters
Volume51
Issue number3
DOIs
Publication statusPublished - 2015 Feb 5

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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