Circuit-level real-time channels like through-silicon vias generally admit only several levels of logic gates for decoding within a clock cycle. From our study two-dimensional parity check has the greatest potential for on-line monitoring and correcting. The bounded rotation scheme for cyclic decoding is first applied in real-time channels with four times of relative correctable cluster size. An unbound rotation scheme is further proposed for higher cluster error correcting capacitance. For an array with a long length H and a narrow width W, the correctable cluster error size can be improved from W to H. From circuit simulation both proposed schemes take only 1.45 ns and 0.76 ns of time penalties respectively. From block error rate analyses under a reasonable coupling model based on conditional probability posterior to additive white Gaussian noised binary symmetric channels, error rate reduction can be improved to 104 times in a 9 dB SNR.
All Science Journal Classification (ASJC) codes
- Modelling and Simulation
- Computer Science Applications
- Electrical and Electronic Engineering