Abstract
As a high-speed circuit-level real-time channel through-silicon vias admit only several levels of logic gates for correcting and repairing within a clock cycle. Unfortunately they are usually arranged as a crowded array for floorplanning and manufacturing reasons. To repair cluster faults and correct cluster errors, in this paper a complete strategy with a fast and adaptive architecture is proposed for built-in self-repairing, correcting and monitoring. The strategy includes off-line built-in self-test/repair and on-line correction, monitoring and repair. An LFSR-based noisy channel emulator is developed for verifying the architecture and evaluating the performance in a magnified probabilistic model. A conditional probability based cluster error model is also developed for analyzing the MTTR and BLER analyses posteriori to the AWGN noise. Evaluations prove that the proposed architecture can be effectively and efficiently suitable for hybrid memory cube to test, repair, detect, correct and monitor a large cluster error almost within a nano-second.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 6th Asia Symposium on Quality Electronic Design, ASQED 2015 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 132-137 |
| Number of pages | 6 |
| ISBN (Electronic) | 9781467374958 |
| DOIs | |
| Publication status | Published - 2015 Sep 21 |
| Event | 6th Asia Symposium on Quality Electronic Design, ASQED 2015 - Kuala Lumpur, Malaysia Duration: 2015 Aug 4 → 2015 Aug 5 |
Other
| Other | 6th Asia Symposium on Quality Electronic Design, ASQED 2015 |
|---|---|
| Country | Malaysia |
| City | Kuala Lumpur |
| Period | 15-08-04 → 15-08-05 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
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Cluster error correction and on-line repair for real-time TSV array. / Huang, Tsung Chu.
Proceedings of the 6th Asia Symposium on Quality Electronic Design, ASQED 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 132-137 7274022.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Cluster error correction and on-line repair for real-time TSV array
AU - Huang, Tsung Chu
PY - 2015/9/21
Y1 - 2015/9/21
N2 - As a high-speed circuit-level real-time channel through-silicon vias admit only several levels of logic gates for correcting and repairing within a clock cycle. Unfortunately they are usually arranged as a crowded array for floorplanning and manufacturing reasons. To repair cluster faults and correct cluster errors, in this paper a complete strategy with a fast and adaptive architecture is proposed for built-in self-repairing, correcting and monitoring. The strategy includes off-line built-in self-test/repair and on-line correction, monitoring and repair. An LFSR-based noisy channel emulator is developed for verifying the architecture and evaluating the performance in a magnified probabilistic model. A conditional probability based cluster error model is also developed for analyzing the MTTR and BLER analyses posteriori to the AWGN noise. Evaluations prove that the proposed architecture can be effectively and efficiently suitable for hybrid memory cube to test, repair, detect, correct and monitor a large cluster error almost within a nano-second.
AB - As a high-speed circuit-level real-time channel through-silicon vias admit only several levels of logic gates for correcting and repairing within a clock cycle. Unfortunately they are usually arranged as a crowded array for floorplanning and manufacturing reasons. To repair cluster faults and correct cluster errors, in this paper a complete strategy with a fast and adaptive architecture is proposed for built-in self-repairing, correcting and monitoring. The strategy includes off-line built-in self-test/repair and on-line correction, monitoring and repair. An LFSR-based noisy channel emulator is developed for verifying the architecture and evaluating the performance in a magnified probabilistic model. A conditional probability based cluster error model is also developed for analyzing the MTTR and BLER analyses posteriori to the AWGN noise. Evaluations prove that the proposed architecture can be effectively and efficiently suitable for hybrid memory cube to test, repair, detect, correct and monitor a large cluster error almost within a nano-second.
UR - http://www.scopus.com/inward/record.url?scp=84962106764&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84962106764&partnerID=8YFLogxK
U2 - 10.1109/ACQED.2015.7274022
DO - 10.1109/ACQED.2015.7274022
M3 - Conference contribution
AN - SCOPUS:84962106764
SP - 132
EP - 137
BT - Proceedings of the 6th Asia Symposium on Quality Electronic Design, ASQED 2015
PB - Institute of Electrical and Electronics Engineers Inc.
ER -