As a high-speed circuit-level real-time channel through-silicon vias admit only several levels of logic gates for correcting and repairing within a clock cycle. Unfortunately they are usually arranged as a crowded array for floorplanning and manufacturing reasons. To repair cluster faults and correct cluster errors, in this paper a complete strategy with a fast and adaptive architecture is proposed for built-in self-repairing, correcting and monitoring. The strategy includes off-line built-in self-test/repair and on-line correction, monitoring and repair. An LFSR-based noisy channel emulator is developed for verifying the architecture and evaluating the performance in a magnified probabilistic model. A conditional probability based cluster error model is also developed for analyzing the MTTR and BLER analyses posteriori to the AWGN noise. Evaluations prove that the proposed architecture can be effectively and efficiently suitable for hybrid memory cube to test, repair, detect, correct and monitor a large cluster error almost within a nano-second.