Clique partitioning based integrated architecture synthesis for VLSI chips

Jer Min Jou, Shiann Rong Kuang, Ren-Der Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The tasks as module selection, scheduling and allocation involved in the architecture synthesis problem of VLSI chips are tightly interdependent. Simultaneous optimization of these tasks is necessary for the global solution of a design. In this paper, we present a new graph model for the integrated architecture synthesis problem of VLSI chips and then formulate the problem as a partial clique partition problem and solve it globally using a heuristic. We have tested our approach using examples from the literature and experimental results show that our approach is better then or as good as other published approaches.

Original languageEnglish
Title of host publication1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages58-62
Number of pages5
ISBN (Electronic)0780309782
DOIs
Publication statusPublished - 1993 Jan 1
Event1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Taipei, Taiwan
Duration: 1993 May 121993 May 14

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)1930-8868

Conference

Conference1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993
CountryTaiwan
CityTaipei
Period93-05-1293-05-14

Fingerprint

very large scale integration
chips
scheduling
synthesis
partitions
modules
Scheduling
optimization

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Jou, J. M., Kuang, S. R., & Chen, R-D. (1993). Clique partitioning based integrated architecture synthesis for VLSI chips. In 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers (pp. 58-62). [263627] (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VTSA.1993.263627
Jou, Jer Min ; Kuang, Shiann Rong ; Chen, Ren-Der. / Clique partitioning based integrated architecture synthesis for VLSI chips. 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 1993. pp. 58-62 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).
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Jou, JM, Kuang, SR & Chen, R-D 1993, Clique partitioning based integrated architecture synthesis for VLSI chips. in 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers., 263627, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 58-62, 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993, Taipei, Taiwan, 93-05-12. https://doi.org/10.1109/VTSA.1993.263627

Clique partitioning based integrated architecture synthesis for VLSI chips. / Jou, Jer Min; Kuang, Shiann Rong; Chen, Ren-Der.

1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 1993. p. 58-62 263627 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Jou JM, Kuang SR, Chen R-D. Clique partitioning based integrated architecture synthesis for VLSI chips. In 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 1993. p. 58-62. 263627. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). https://doi.org/10.1109/VTSA.1993.263627