Abstract
This paper presents BIFEST, an ATPG system that employs the built-in intermediate voltage test technique in an efficient ATPG process to deal with CMOS bridging faults. Fast and accurate calculations of the intermediate bridging voltages and the variant threshold tolerance margins on a resistive bridging fault model are presented. A PODEM-like, PPSFP-based ATPG process is developed to generate test patterns for faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits, called built-in intermediate voltage sensors (BIVSs). By this methodology, almost the same fault coverage as that employing IDOQ testing can be achieved with only logic monitoring required.
| Original language | English |
|---|---|
| Pages (from-to) | 194-218 |
| Number of pages | 25 |
| Journal | ACM Transactions on Design Automation of Electronic Systems |
| Volume | 4 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 1999 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
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BIFEST : A built-in intermediate fault effect sensing and test generation system for cmos bridging faults. / Lee, Kuen Jong; Tang, Jing Jou; Huang, Tsung-Chu.
In: ACM Transactions on Design Automation of Electronic Systems, Vol. 4, No. 2, 01.01.1999, p. 194-218.Research output: Contribution to journal › Article
TY - JOUR
T1 - BIFEST
T2 - A built-in intermediate fault effect sensing and test generation system for cmos bridging faults
AU - Lee, Kuen Jong
AU - Tang, Jing Jou
AU - Huang, Tsung-Chu
PY - 1999/1/1
Y1 - 1999/1/1
N2 - This paper presents BIFEST, an ATPG system that employs the built-in intermediate voltage test technique in an efficient ATPG process to deal with CMOS bridging faults. Fast and accurate calculations of the intermediate bridging voltages and the variant threshold tolerance margins on a resistive bridging fault model are presented. A PODEM-like, PPSFP-based ATPG process is developed to generate test patterns for faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits, called built-in intermediate voltage sensors (BIVSs). By this methodology, almost the same fault coverage as that employing IDOQ testing can be achieved with only logic monitoring required.
AB - This paper presents BIFEST, an ATPG system that employs the built-in intermediate voltage test technique in an efficient ATPG process to deal with CMOS bridging faults. Fast and accurate calculations of the intermediate bridging voltages and the variant threshold tolerance margins on a resistive bridging fault model are presented. A PODEM-like, PPSFP-based ATPG process is developed to generate test patterns for faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits, called built-in intermediate voltage sensors (BIVSs). By this methodology, almost the same fault coverage as that employing IDOQ testing can be achieved with only logic monitoring required.
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UR - http://www.scopus.com/inward/citedby.url?scp=22644448915&partnerID=8YFLogxK
U2 - 10.1145/307988.307992
DO - 10.1145/307988.307992
M3 - Article
AN - SCOPUS:22644448915
VL - 4
SP - 194
EP - 218
JO - ACM Transactions on Design Automation of Electronic Systems
JF - ACM Transactions on Design Automation of Electronic Systems
SN - 1084-4309
IS - 2
ER -