BIFEST: A built-in intermediate fault effect sensing and test generation system for cmos bridging faults

Kuen Jong Lee, Jing Jou Tang, Tsung-Chu Huang

Research output: Contribution to journalArticle

1 Citation (Scopus)


This paper presents BIFEST, an ATPG system that employs the built-in intermediate voltage test technique in an efficient ATPG process to deal with CMOS bridging faults. Fast and accurate calculations of the intermediate bridging voltages and the variant threshold tolerance margins on a resistive bridging fault model are presented. A PODEM-like, PPSFP-based ATPG process is developed to generate test patterns for faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits, called built-in intermediate voltage sensors (BIVSs). By this methodology, almost the same fault coverage as that employing IDOQ testing can be achieved with only logic monitoring required.

Original languageEnglish
Pages (from-to)194-218
Number of pages25
JournalACM Transactions on Design Automation of Electronic Systems
Issue number2
Publication statusPublished - 1999 Jan 1


All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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