An ultra-low temperature-coefficient CMOS voltage reference

H. C. Lai, Z. M. Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A CMOS voltage reference, which is based on the same magnitude of gate-source voltage of an NMOS and a PMOS operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in TSMC 0.18 μm CMOS process. The effect area is only 18 μ m × 25 μ m. It gives a temperature coefficient of not greater than 0.68 ppm/°C from -70°C to 150°C without trimming, while consuming a maximum of 1 μ A with a supply voltage of 0.9 V.

Original languageEnglish
Title of host publicationIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Pages369-372
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
EventIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan
Duration: 2007 Dec 202007 Dec 22

Other

OtherIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
CountryTaiwan
CityTainan
Period07-12-2007-12-22

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Lai, H. C., & Lin, Z. M. (2007). An ultra-low temperature-coefficient CMOS voltage reference. In IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 (pp. 369-372). [4450139] https://doi.org/10.1109/EDSSC.2007.4450139