An optimization design in the HV nLDMOS by Taguchi method

Shen Li Chen; Tzung Shian Wu; Yun Ru Chen; Hung Wei Chen; Chun Hsing Shih; H. H. Chen

doi:10.4028/www.scientific.net/AMR.482-484.81

An optimization design in the HV nLDMOS by Taguchi method

Shen Li Chen, Tzung Shian Wu, Yun Ru Chen, Hung Wei Chen, Chun Hsing Shih, H. H. Chen

Department of Electronic Engineering

Research output: Contribution to journal › Conference article

1 Citation (Scopus)

Abstract

This paper applied the Taguchi method to simulate the latch-up effect of nLDMOS to achieve an optimization design. The applied model is for an nLDMOS structure with high voltage well plus the adaptive (adjustment) layers of source & drain, and an N-type buried layer. Although the methods we could choose is abundant, we hope to effectively obtain the data which is useful for statistics in order to judge the correct characteristic of parameters. We applied the Taguchi method to perform an optimization in the paper. There are six parameters with two levels in this work, so we choose the Taguchi table to be L ₈(2 ⁷). By this way, it can decrease the times of experiment much effectively.

Original language	English
Pages (from-to)	81-84
Number of pages	4
Journal	Advanced Materials Research
Volume	482-484
DOIs	https://doi.org/10.4028/www.scientific.net/AMR.482-484.81
Publication status	Published - 2012 Apr 4
Event	3rd international Conference on Manufacturing Science and Engineering, ICMSE 2012 - Xiamen, China Duration: 2012 Mar 27 → 2012 Mar 29

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All Science Journal Classification (ASJC) codes

Engineering(all)

Cite this

Chen, S. L., Wu, T. S., Chen, Y. R., Chen, H. W., Shih, C. H., & Chen, H. H. (2012). An optimization design in the HV nLDMOS by Taguchi method. Advanced Materials Research, 482-484, 81-84. https://doi.org/10.4028/www.scientific.net/AMR.482-484.81

@article{cc3e823503c8425f85b0601b2b9872c5,

title = "An optimization design in the HV nLDMOS by Taguchi method",

abstract = "This paper applied the Taguchi method to simulate the latch-up effect of nLDMOS to achieve an optimization design. The applied model is for an nLDMOS structure with high voltage well plus the adaptive (adjustment) layers of source & drain, and an N-type buried layer. Although the methods we could choose is abundant, we hope to effectively obtain the data which is useful for statistics in order to judge the correct characteristic of parameters. We applied the Taguchi method to perform an optimization in the paper. There are six parameters with two levels in this work, so we choose the Taguchi table to be L 8(2 7). By this way, it can decrease the times of experiment much effectively.",

author = "Chen, {Shen Li} and Wu, {Tzung Shian} and Chen, {Yun Ru} and Chen, {Hung Wei} and Shih, {Chun Hsing} and Chen, {H. H.}",

year = "2012",

month = apr

day = "4",

doi = "10.4028/www.scientific.net/AMR.482-484.81",

language = "English",

volume = "482-484",

pages = "81--84",

journal = "Advanced Materials Research",

issn = "1022-6680",

publisher = "Trans Tech Publications",

note = "3rd international Conference on Manufacturing Science and Engineering, ICMSE 2012 ; Conference date: 27-03-2012 Through 29-03-2012",

}

TY - JOUR

T1 - An optimization design in the HV nLDMOS by Taguchi method

AU - Chen, Shen Li

AU - Wu, Tzung Shian

AU - Chen, Yun Ru

AU - Chen, Hung Wei

AU - Shih, Chun Hsing

AU - Chen, H. H.

PY - 2012/4/4

Y1 - 2012/4/4

N2 - This paper applied the Taguchi method to simulate the latch-up effect of nLDMOS to achieve an optimization design. The applied model is for an nLDMOS structure with high voltage well plus the adaptive (adjustment) layers of source & drain, and an N-type buried layer. Although the methods we could choose is abundant, we hope to effectively obtain the data which is useful for statistics in order to judge the correct characteristic of parameters. We applied the Taguchi method to perform an optimization in the paper. There are six parameters with two levels in this work, so we choose the Taguchi table to be L 8(2 7). By this way, it can decrease the times of experiment much effectively.

AB - This paper applied the Taguchi method to simulate the latch-up effect of nLDMOS to achieve an optimization design. The applied model is for an nLDMOS structure with high voltage well plus the adaptive (adjustment) layers of source & drain, and an N-type buried layer. Although the methods we could choose is abundant, we hope to effectively obtain the data which is useful for statistics in order to judge the correct characteristic of parameters. We applied the Taguchi method to perform an optimization in the paper. There are six parameters with two levels in this work, so we choose the Taguchi table to be L 8(2 7). By this way, it can decrease the times of experiment much effectively.

UR - http://www.scopus.com/inward/record.url?scp=84859170732&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84859170732&partnerID=8YFLogxK

U2 - 10.4028/www.scientific.net/AMR.482-484.81

DO - 10.4028/www.scientific.net/AMR.482-484.81

M3 - Conference article

AN - SCOPUS:84859170732

VL - 482-484

SP - 81

EP - 84

JO - Advanced Materials Research

JF - Advanced Materials Research

SN - 1022-6680

T2 - 3rd international Conference on Manufacturing Science and Engineering, ICMSE 2012

Y2 - 27 March 2012 through 29 March 2012

ER -

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10.4028/www.scientific.net/AMR.482-484.81