An interleaving technique for reducing peak power in multiple-chain scan circuits during test application

Kuen Jong Lee, Tsung Chu Huang

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is developed which can significantly reduce the peak power. This method can be efficiently integrated with a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. Up to 51% peak power reduction can be achieved when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, up to 76% of peak-power reduction is observed.

Original languageEnglish
Pages (from-to)627-636
Number of pages10
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume18
Issue number6
DOIs
Publication statusPublished - 2002 Dec 1

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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