Abstract
-Different from the previous PLA folding algorithms which perform row and column foldings independently, we propose an algorithm to obtain bipartite row or column folding result on the same graph. The PLA personality matrix is modeled as a graph and the folding problem is modeled as a partitioning problem. Experimental results show that this algorithm can lead a good guide to select row or column folding for reducing the chip area of the PLA efficiently.
| Original language | English |
|---|---|
| Pages (from-to) | 494-498 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications |
| Volume | 41 |
| Issue number | 7 |
| DOIs | |
| Publication status | Published - 1994 Jan 1 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
}
An Efficient Algorithm for Selecting Bipartite Row or Column Folding of Programmable Logic Arrays. / Liu, Bin Da; wei, kai-cheng.
In: IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 41, No. 7, 01.01.1994, p. 494-498.Research output: Contribution to journal › Article
TY - JOUR
T1 - An Efficient Algorithm for Selecting Bipartite Row or Column Folding of Programmable Logic Arrays
AU - Liu, Bin Da
AU - wei, kai-cheng
PY - 1994/1/1
Y1 - 1994/1/1
N2 - -Different from the previous PLA folding algorithms which perform row and column foldings independently, we propose an algorithm to obtain bipartite row or column folding result on the same graph. The PLA personality matrix is modeled as a graph and the folding problem is modeled as a partitioning problem. Experimental results show that this algorithm can lead a good guide to select row or column folding for reducing the chip area of the PLA efficiently.
AB - -Different from the previous PLA folding algorithms which perform row and column foldings independently, we propose an algorithm to obtain bipartite row or column folding result on the same graph. The PLA personality matrix is modeled as a graph and the folding problem is modeled as a partitioning problem. Experimental results show that this algorithm can lead a good guide to select row or column folding for reducing the chip area of the PLA efficiently.
UR - http://www.scopus.com/inward/record.url?scp=0028464686&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0028464686&partnerID=8YFLogxK
U2 - 10.1109/81.298365
DO - 10.1109/81.298365
M3 - Article
AN - SCOPUS:0028464686
VL - 41
SP - 494
EP - 498
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
SN - 1549-8328
IS - 7
ER -