Abstract
This paper provides an arithmetic controller comprising: an arithmetic logic unit having a plurality of arithmetic instructions, such as ADD (Addition), SUB (Subtraction), MUL (Multiplication), and DIV (Division) instructions. This arithmetic processor was implemented by a cell-based flow and supports the basic mathematical operations, and numerical control. All mathematical instructions are composed of three bytes. In: the first byte, it contains the operation code and the address of the operand, while the operands are in the second and third bytes. While the processor architecture compared with the conventional CPU, the performance is speed up for the number reduction of instruction cycle. The number of instruction cycle is decreased to five T-states. All of these circuits were implemented by the TSMC 0.35 μm cell library. A 20-pin I/O PAD was selected to package this processor. The experimental results are showed and discussions are made.
| Original language | English |
|---|---|
| Pages (from-to) | 2045-2052 |
| Number of pages | 8 |
| Journal | Computers and Electrical Engineering |
| Volume | 39 |
| Issue number | 7 |
| DOIs | |
| Publication status | Published - 2013 Oct 1 |
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All Science Journal Classification (ASJC) codes
- Control and Systems Engineering
- Computer Science(all)
- Electrical and Electronic Engineering
Cite this
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An arithmetic controller design for numerical control. / Yi, Shu-chung; Hsieh, Chin Fa.
In: Computers and Electrical Engineering, Vol. 39, No. 7, 01.10.2013, p. 2045-2052.Research output: Contribution to journal › Article
TY - JOUR
T1 - An arithmetic controller design for numerical control
AU - Yi, Shu-chung
AU - Hsieh, Chin Fa
PY - 2013/10/1
Y1 - 2013/10/1
N2 - This paper provides an arithmetic controller comprising: an arithmetic logic unit having a plurality of arithmetic instructions, such as ADD (Addition), SUB (Subtraction), MUL (Multiplication), and DIV (Division) instructions. This arithmetic processor was implemented by a cell-based flow and supports the basic mathematical operations, and numerical control. All mathematical instructions are composed of three bytes. In: the first byte, it contains the operation code and the address of the operand, while the operands are in the second and third bytes. While the processor architecture compared with the conventional CPU, the performance is speed up for the number reduction of instruction cycle. The number of instruction cycle is decreased to five T-states. All of these circuits were implemented by the TSMC 0.35 μm cell library. A 20-pin I/O PAD was selected to package this processor. The experimental results are showed and discussions are made.
AB - This paper provides an arithmetic controller comprising: an arithmetic logic unit having a plurality of arithmetic instructions, such as ADD (Addition), SUB (Subtraction), MUL (Multiplication), and DIV (Division) instructions. This arithmetic processor was implemented by a cell-based flow and supports the basic mathematical operations, and numerical control. All mathematical instructions are composed of three bytes. In: the first byte, it contains the operation code and the address of the operand, while the operands are in the second and third bytes. While the processor architecture compared with the conventional CPU, the performance is speed up for the number reduction of instruction cycle. The number of instruction cycle is decreased to five T-states. All of these circuits were implemented by the TSMC 0.35 μm cell library. A 20-pin I/O PAD was selected to package this processor. The experimental results are showed and discussions are made.
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UR - http://www.scopus.com/inward/citedby.url?scp=84885600675&partnerID=8YFLogxK
U2 - 10.1016/j.compeleceng.2013.06.002
DO - 10.1016/j.compeleceng.2013.06.002
M3 - Article
AN - SCOPUS:84885600675
VL - 39
SP - 2045
EP - 2052
JO - Computers and Electrical Engineering
JF - Computers and Electrical Engineering
SN - 0045-7906
IS - 7
ER -