An 8-bit current-steering digital to analog converter

Shu-chung Yi

doi:10.1016/j.aeue.2011.10.003

An 8-bit current-steering digital to analog converter

Shu-chung Yi

Department of Computer Science and Information Engineering

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

In this paper, an 8-bit current steering digital-to-analog converter is proposed. The digital-to-analog converter contained four sets of current mirrors with different weight. The digital-to-analog converter was implemented using TSMC 0.35 μm, 2P4M CMOS process. The average INL and DNL are 0.27 LSB and 0.32 LSB, respectively. At the sample rate of 100 MHz and supply voltage of 3.3 V, the DAC consumed about 27.6 mW. The SFDR was 50.9 dB. The core size is 0.024 mm ². The digital-to-analog converter of this construction consumed less power and chip area. It is suitable for portable device application.

Original language	English
Pages (from-to)	433-437
Number of pages	5
Journal	AEU - International Journal of Electronics and Communications
Volume	66
Issue number	5
DOIs	https://doi.org/10.1016/j.aeue.2011.10.003
Publication status	Published - 2012 May 1

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1016/j.aeue.2011.10.003

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AB - In this paper, an 8-bit current steering digital-to-analog converter is proposed. The digital-to-analog converter contained four sets of current mirrors with different weight. The digital-to-analog converter was implemented using TSMC 0.35 μm, 2P4M CMOS process. The average INL and DNL are 0.27 LSB and 0.32 LSB, respectively. At the sample rate of 100 MHz and supply voltage of 3.3 V, the DAC consumed about 27.6 mW. The SFDR was 50.9 dB. The core size is 0.024 mm 2. The digital-to-analog converter of this construction consumed less power and chip area. It is suitable for portable device application.

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