Abstract
In this paper, an 8-bit current steering digital-to-analog converter is proposed. The digital-to-analog converter contained four sets of current mirrors with different weight. The digital-to-analog converter was implemented using TSMC 0.35 μm, 2P4M CMOS process. The average INL and DNL are 0.27 LSB and 0.32 LSB, respectively. At the sample rate of 100 MHz and supply voltage of 3.3 V, the DAC consumed about 27.6 mW. The SFDR was 50.9 dB. The core size is 0.024 mm 2. The digital-to-analog converter of this construction consumed less power and chip area. It is suitable for portable device application.
| Original language | English |
|---|---|
| Pages (from-to) | 433-437 |
| Number of pages | 5 |
| Journal | AEU - International Journal of Electronics and Communications |
| Volume | 66 |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - 2012 May 1 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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An 8-bit current-steering digital to analog converter. / Yi, Shu-chung.
In: AEU - International Journal of Electronics and Communications, Vol. 66, No. 5, 01.05.2012, p. 433-437.Research output: Contribution to journal › Article
TY - JOUR
T1 - An 8-bit current-steering digital to analog converter
AU - Yi, Shu-chung
PY - 2012/5/1
Y1 - 2012/5/1
N2 - In this paper, an 8-bit current steering digital-to-analog converter is proposed. The digital-to-analog converter contained four sets of current mirrors with different weight. The digital-to-analog converter was implemented using TSMC 0.35 μm, 2P4M CMOS process. The average INL and DNL are 0.27 LSB and 0.32 LSB, respectively. At the sample rate of 100 MHz and supply voltage of 3.3 V, the DAC consumed about 27.6 mW. The SFDR was 50.9 dB. The core size is 0.024 mm 2. The digital-to-analog converter of this construction consumed less power and chip area. It is suitable for portable device application.
AB - In this paper, an 8-bit current steering digital-to-analog converter is proposed. The digital-to-analog converter contained four sets of current mirrors with different weight. The digital-to-analog converter was implemented using TSMC 0.35 μm, 2P4M CMOS process. The average INL and DNL are 0.27 LSB and 0.32 LSB, respectively. At the sample rate of 100 MHz and supply voltage of 3.3 V, the DAC consumed about 27.6 mW. The SFDR was 50.9 dB. The core size is 0.024 mm 2. The digital-to-analog converter of this construction consumed less power and chip area. It is suitable for portable device application.
UR - http://www.scopus.com/inward/record.url?scp=84858698032&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84858698032&partnerID=8YFLogxK
U2 - 10.1016/j.aeue.2011.10.003
DO - 10.1016/j.aeue.2011.10.003
M3 - Article
AN - SCOPUS:84858698032
VL - 66
SP - 433
EP - 437
JO - AEU - International Journal of Electronics and Communications
JF - AEU - International Journal of Electronics and Communications
SN - 1434-8411
IS - 5
ER -