An 8-bit 1.42GS/s 0.54mW CMOS Flash ADC

You Yi Hsieh, Zhi-Ming Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents an 8-bit Flash Analog-to-Digital converter (ADC) implemented in 0.18-m CMOS process. Different from the conventional Flash ADCs, we use a single MOS comparator technique to replace the traditional comparator. Therefore, our method can reduce a lot of transistor numbers, chip area, power consumption for higher resolution. The designed Flash ADC consumes only 0.54 mW from a 1.8V power supply. The speed of this design is 1.4GS/s. The simulated static differential non-linearity error (DNL) and integral non-linearity error (INL) are between 0.4/0.4 LSB and 0.42/0.55 LSB, respectively.

Original languageEnglish
Title of host publicationICICS 2011 - 8th International Conference on Information, Communications and Signal Processing
DOIs
Publication statusPublished - 2011 Dec 1
Event8th International Conference on Information, Communications and Signal Processing, ICICS 2011 - Singapore, Singapore
Duration: 2011 Dec 132011 Dec 16

Publication series

NameICICS 2011 - 8th International Conference on Information, Communications and Signal Processing

Other

Other8th International Conference on Information, Communications and Signal Processing, ICICS 2011
CountrySingapore
CitySingapore
Period11-12-1311-12-16

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All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Information Systems
  • Signal Processing

Cite this

Hsieh, Y. Y., & Lin, Z-M. (2011). An 8-bit 1.42GS/s 0.54mW CMOS Flash ADC. In ICICS 2011 - 8th International Conference on Information, Communications and Signal Processing [6173519] (ICICS 2011 - 8th International Conference on Information, Communications and Signal Processing). https://doi.org/10.1109/ICICS.2011.6173519