Abstract
In this paper, a 1.2-V 10-GHz low-power low-noise VCO is designed and fabricated in a 0.18μm CMOS process. By using noise-reduction techniques associated with the current-reused structure, the VCO can achieve lower power consumption and phase noise. The simulated power consumption is 0.88-mW. The simulated phase noise is -114.8- dBc/Hz at 1-MHz offset frequencies. The attained FOM is - 191.
| Original language | English |
|---|---|
| Title of host publication | 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09 |
| Pages | 1063-1066 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2009 Dec 1 |
| Event | 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09 - Cancun, Mexico Duration: 2009 Aug 2 → 2009 Aug 5 |
Publication series
| Name | Midwest Symposium on Circuits and Systems |
|---|---|
| ISSN (Print) | 1548-3746 |
Other
| Other | 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09 |
|---|---|
| Country | Mexico |
| City | Cancun |
| Period | 09-08-02 → 09-08-05 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
}
A10-GHz 0.88-mW low-phase-noise CMOS VCO. / Syu, Jin Rong; Lin, Zhi-Ming.
2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09. 2009. p. 1063-1066 5235985 (Midwest Symposium on Circuits and Systems).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A10-GHz 0.88-mW low-phase-noise CMOS VCO
AU - Syu, Jin Rong
AU - Lin, Zhi-Ming
PY - 2009/12/1
Y1 - 2009/12/1
N2 - In this paper, a 1.2-V 10-GHz low-power low-noise VCO is designed and fabricated in a 0.18μm CMOS process. By using noise-reduction techniques associated with the current-reused structure, the VCO can achieve lower power consumption and phase noise. The simulated power consumption is 0.88-mW. The simulated phase noise is -114.8- dBc/Hz at 1-MHz offset frequencies. The attained FOM is - 191.
AB - In this paper, a 1.2-V 10-GHz low-power low-noise VCO is designed and fabricated in a 0.18μm CMOS process. By using noise-reduction techniques associated with the current-reused structure, the VCO can achieve lower power consumption and phase noise. The simulated power consumption is 0.88-mW. The simulated phase noise is -114.8- dBc/Hz at 1-MHz offset frequencies. The attained FOM is - 191.
UR - http://www.scopus.com/inward/record.url?scp=77950663048&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77950663048&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2009.5235985
DO - 10.1109/MWSCAS.2009.5235985
M3 - Conference contribution
AN - SCOPUS:77950663048
SN - 9781424444793
T3 - Midwest Symposium on Circuits and Systems
SP - 1063
EP - 1066
BT - 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09
ER -