A10-GHz 0.88-mW low-phase-noise CMOS VCO

Jin Rong Syu, Zhi-Ming Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, a 1.2-V 10-GHz low-power low-noise VCO is designed and fabricated in a 0.18μm CMOS process. By using noise-reduction techniques associated with the current-reused structure, the VCO can achieve lower power consumption and phase noise. The simulated power consumption is 0.88-mW. The simulated phase noise is -114.8- dBc/Hz at 1-MHz offset frequencies. The attained FOM is - 191.

Original languageEnglish
Title of host publication2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09
Pages1063-1066
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09 - Cancun, Mexico
Duration: 2009 Aug 22009 Aug 5

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09
CountryMexico
CityCancun
Period09-08-0209-08-05

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Syu, J. R., & Lin, Z-M. (2009). A10-GHz 0.88-mW low-phase-noise CMOS VCO. In 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09 (pp. 1063-1066). [5235985] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2009.5235985