A VLSI design with built-in SRAM arrays for implementing full search block matching algorithm

Tsung Yi Wu; Kuang Yao Chen; Shi Yi Huang; Tai Lun Li; How Rern Lin

doi:10.1109/ISCE.2009.5156949

A VLSI design with built-in SRAM arrays for implementing full search block matching algorithm

Tsung Yi Wu, Kuang Yao Chen, Shi Yi Huang, Tai Lun Li, How Rern Lin

Department of Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A conventional 2-dimensional (2-D) systolic processing element (PE) array of a chip used for implementing Full Search Block Matching Algorithm (FSBMA) needs a large number of input pads to read sequence image data from SRAM chips. In our work, we embed SRAMs in the FSBMA chip and the PEs read the sequence image data from the embedded SRAMs quickly and directly. Three embedded SRAM arrays are used to store a current frame, a reference frame, and a prefetch frame. Our chip only needs 8 input pads to read off-chip image data. Experimental results show that our proposed chip can process 704 frames per second for the CIF format. By extending the SRAM arrays, our proposed chip can process 34 frames per second for the HDTV resolution.

Original language	English
Title of host publication	2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009
Pages	619-621
Number of pages	3
DOIs	https://doi.org/10.1109/ISCE.2009.5156949
Publication status	Published - 2009 Oct 27
Event	2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009 - Kyoto, Japan Duration: 2009 May 25 → 2009 May 28

Publication series

Name	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)	0747-668X

Other

Other	2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009
Country	Japan
City	Kyoto
Period	09-05-25 → 09-05-28

All Science Journal Classification (ASJC) codes

Industrial and Manufacturing Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ISCE.2009.5156949

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Wu, T. Y., Chen, K. Y., Huang, S. Y., Li, T. L., & Lin, H. R. (2009). A VLSI design with built-in SRAM arrays for implementing full search block matching algorithm. In 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009 (pp. 619-621). [5156949] (Digest of Technical Papers - IEEE International Conference on Consumer Electronics). https://doi.org/10.1109/ISCE.2009.5156949

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title = "A VLSI design with built-in SRAM arrays for implementing full search block matching algorithm",

abstract = "A conventional 2-dimensional (2-D) systolic processing element (PE) array of a chip used for implementing Full Search Block Matching Algorithm (FSBMA) needs a large number of input pads to read sequence image data from SRAM chips. In our work, we embed SRAMs in the FSBMA chip and the PEs read the sequence image data from the embedded SRAMs quickly and directly. Three embedded SRAM arrays are used to store a current frame, a reference frame, and a prefetch frame. Our chip only needs 8 input pads to read off-chip image data. Experimental results show that our proposed chip can process 704 frames per second for the CIF format. By extending the SRAM arrays, our proposed chip can process 34 frames per second for the HDTV resolution.",

author = "Wu, {Tsung Yi} and Chen, {Kuang Yao} and Huang, {Shi Yi} and Li, {Tai Lun} and Lin, {How Rern}",

year = "2009",

month = oct,

day = "27",

doi = "10.1109/ISCE.2009.5156949",

language = "English",

isbn = "9781424429769",

series = "Digest of Technical Papers - IEEE International Conference on Consumer Electronics",

pages = "619--621",

booktitle = "2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009",

note = "2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009 ; Conference date: 25-05-2009 Through 28-05-2009",

}

Wu, TY, Chen, KY, Huang, SY, Li, TL & Lin, HR 2009, A VLSI design with built-in SRAM arrays for implementing full search block matching algorithm. in 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009., 5156949, Digest of Technical Papers - IEEE International Conference on Consumer Electronics, pp. 619-621, 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009, Kyoto, Japan, 09-05-25. https://doi.org/10.1109/ISCE.2009.5156949

A VLSI design with built-in SRAM arrays for implementing full search block matching algorithm. / Wu, Tsung Yi; Chen, Kuang Yao; Huang, Shi Yi; Li, Tai Lun; Lin, How Rern.

2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009. 2009. p. 619-621 5156949 (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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