Abstract
A conventional 2-dimensional (2-D) systolic processing element (PE) array of a chip used for implementing Full Search Block Matching Algorithm (FSBMA) needs a large number of input pads to read sequence image data from SRAM chips. In our work, we embed SRAMs in the FSBMA chip and the PEs read the sequence image data from the embedded SRAMs quickly and directly. Three embedded SRAM arrays are used to store a current frame, a reference frame, and a prefetch frame. Our chip only needs 8 input pads to read off-chip image data. Experimental results show that our proposed chip can process 704 frames per second for the CIF format. By extending the SRAM arrays, our proposed chip can process 34 frames per second for the HDTV resolution.
| Original language | English |
|---|---|
| Title of host publication | 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009 |
| Pages | 619-621 |
| Number of pages | 3 |
| DOIs | |
| Publication status | Published - 2009 Oct 27 |
| Event | 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009 - Kyoto, Japan Duration: 2009 May 25 → 2009 May 28 |
Publication series
| Name | Digest of Technical Papers - IEEE International Conference on Consumer Electronics |
|---|---|
| ISSN (Print) | 0747-668X |
Other
| Other | 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009 |
|---|---|
| Country | Japan |
| City | Kyoto |
| Period | 09-05-25 → 09-05-28 |
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All Science Journal Classification (ASJC) codes
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering
Cite this
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A VLSI design with built-in SRAM arrays for implementing full search block matching algorithm. / Wu, Tsung Yi; Chen, Kuang Yao; Huang, Shi Yi; Li, Tai Lun; Lin, How Rern.
2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009. 2009. p. 619-621 5156949 (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A VLSI design with built-in SRAM arrays for implementing full search block matching algorithm
AU - Wu, Tsung Yi
AU - Chen, Kuang Yao
AU - Huang, Shi Yi
AU - Li, Tai Lun
AU - Lin, How Rern
PY - 2009/10/27
Y1 - 2009/10/27
N2 - A conventional 2-dimensional (2-D) systolic processing element (PE) array of a chip used for implementing Full Search Block Matching Algorithm (FSBMA) needs a large number of input pads to read sequence image data from SRAM chips. In our work, we embed SRAMs in the FSBMA chip and the PEs read the sequence image data from the embedded SRAMs quickly and directly. Three embedded SRAM arrays are used to store a current frame, a reference frame, and a prefetch frame. Our chip only needs 8 input pads to read off-chip image data. Experimental results show that our proposed chip can process 704 frames per second for the CIF format. By extending the SRAM arrays, our proposed chip can process 34 frames per second for the HDTV resolution.
AB - A conventional 2-dimensional (2-D) systolic processing element (PE) array of a chip used for implementing Full Search Block Matching Algorithm (FSBMA) needs a large number of input pads to read sequence image data from SRAM chips. In our work, we embed SRAMs in the FSBMA chip and the PEs read the sequence image data from the embedded SRAMs quickly and directly. Three embedded SRAM arrays are used to store a current frame, a reference frame, and a prefetch frame. Our chip only needs 8 input pads to read off-chip image data. Experimental results show that our proposed chip can process 704 frames per second for the CIF format. By extending the SRAM arrays, our proposed chip can process 34 frames per second for the HDTV resolution.
UR - http://www.scopus.com/inward/record.url?scp=70350225980&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70350225980&partnerID=8YFLogxK
U2 - 10.1109/ISCE.2009.5156949
DO - 10.1109/ISCE.2009.5156949
M3 - Conference contribution
AN - SCOPUS:70350225980
SN - 9781424429769
T3 - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
SP - 619
EP - 621
BT - 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009
ER -