A VLSI architecture for image coding using EZW algorithm

Po-Yueh Chen, Tinku Acharya

Research output: Contribution to journalArticle

Abstract

Embedded image coding has drawn a lot of attention since Shapiro's publication of his works on embedded zerotree wavelet (EZW). In this paper, we present an architecture for the embedded zerotree wavelet algorithm. This architecture is very suitable for VLSI implementation and much faster than software implementation on a general-purpose computer. Integration of this EZW architecture with our previously proposed systolic architectures for discrete wavelet transform (DWT) provides a high performance architecture for image compression.

Original languageEnglish
Pages (from-to)87-94
Number of pages8
JournalInternational Journal of Robotics and Automation
Volume13
Issue number3
Publication statusPublished - 1998 Dec 1

Fingerprint

VLSI Architecture
General purpose computers
Image Coding
Discrete wavelet transforms
Image compression
Image coding
Wavelets
Image Compression
Wavelet Transform
High Performance
Architecture
Software

All Science Journal Classification (ASJC) codes

  • Software
  • Control and Systems Engineering
  • Modelling and Simulation
  • Mechanical Engineering
  • Electrical and Electronic Engineering
  • Artificial Intelligence

Cite this

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A VLSI architecture for image coding using EZW algorithm. / Chen, Po-Yueh; Acharya, Tinku.

In: International Journal of Robotics and Automation, Vol. 13, No. 3, 01.12.1998, p. 87-94.

Research output: Contribution to journalArticle

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