A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling

Tsung Chu Huang, Jing Chi Tzeng, Yuan Wei Chao, Ji Jan Chen, Wei Ting Liu, Kuen Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
Original languageEnglish
Title of host publication2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages167-170
Number of pages4
DOIs
Publication statusPublished - 2007 Oct 1
Event2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan
Duration: 2007 Apr 262007 Apr 28

Other

Other2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
CountryTaiwan
CityHsinchu
Period07-04-2607-04-28

Fingerprint

Scheduling
Power management

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Huang, T. C., Tzeng, J. C., Chao, Y. W., Chen, J. J., Liu, W. T., & Lee, K. J. (2007). A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 167-170). [4027523] https://doi.org/10.1109/VDAT.2006.258151
Huang, Tsung Chu ; Tzeng, Jing Chi ; Chao, Yuan Wei ; Chen, Ji Jan ; Liu, Wei Ting ; Lee, Kuen Jong. / A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling. 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. pp. 167-170
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Huang, TC, Tzeng, JC, Chao, YW, Chen, JJ, Liu, WT & Lee, KJ 2007, A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling. in 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers., 4027523, pp. 167-170, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, Hsinchu, Taiwan, 07-04-26. https://doi.org/10.1109/VDAT.2006.258151

A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling. / Huang, Tsung Chu; Tzeng, Jing Chi; Chao, Yuan Wei; Chen, Ji Jan; Liu, Wei Ting; Lee, Kuen Jong.

2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 167-170 4027523.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Huang TC, Tzeng JC, Chao YW, Chen JJ, Liu WT, Lee KJ. A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 167-170. 4027523 https://doi.org/10.1109/VDAT.2006.258151