A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling

Tsung Chu Huang, Jing Chi Tzeng, Yuan Wei Chao, Ji Jan Chen, Wei Ting Liu, Kuen Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
Original languageEnglish
Title of host publication2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages167-170
Number of pages4
DOIs
Publication statusPublished - 2007 Oct 1
Event2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan
Duration: 2007 Apr 262007 Apr 28

Publication series

Name2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Other

Other2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
CountryTaiwan
CityHsinchu
Period07-04-2607-04-28

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Huang, T. C., Tzeng, J. C., Chao, Y. W., Chen, J. J., Liu, W. T., & Lee, K. J. (2007). A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 167-170). [4027523] (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258151