The memory issue plays a very important role for the performance evaluation of a design of 2-Dimensional Discrete Wavelet Transform (2DDWT). A traditional 2DDWT architecture generally needs DRAM to store the input pixel and memory to store temporary results between the row and column processors. In this article, we present a system on a chip (SoC) for video/image processing. The chip integrates an analog-to-digital converter (ADC) with a highly efficient-memory 2DDWT. The latter one contains two main components only: a row processor and a column processor. With this integrated chip plus the use of feedback shift registers (FSR) in the column processor, the architecture we propose can disuse the DRAM and reduce the memory. The pipelined technique is also utilized in the proposed 2DDWT to shorten the critical path to an adder delay. Our architecture outperforms the existing architectures in that it uses less memory size and has low control complexity. It needs only a 2N register instead of a 3.5N register of traditional architectures for a one-level 2DDWT of the 5/3 Lifting-based Discrete Wavelet Transform (LDWT) in an N x N image. Our 2DDWT architecture is coded in VerilogHDL and the Synopsys Design Compiler is employed to synthesize the design with the standard-cell from TSMC 0.18 μm cell library for verification. The ADC is designed by a full-custom methodology, plays as an IP of the SoC. With the integrated SoC, based on the mix-mode design flow, the proposed work requires no external memory, which accordingly reduces the power consumption by memory access and 20 I/O PADs, it also reduces the printed circuit board (PCB) size. Moreover, the proposed SoC supports the resolution of 10 bits and can easily integrate further with the CMOS image sensor (CIS) or other IPs. This, then, completes a single chip and which is ready for a real-time wavelet-based video coding.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering