A rapid acquisition phase-locked loop with frequency-double circuit operated in 2.4-GHZ band

Ming Feng Wu, Zhi Ming Lin, Jun Da Chen, Kuan Hung Liu

Research output: Contribution to conferencePaper

Abstract

This paper proposed a rapid acquisition phase-locked loop for 2.4-GHz frequency band. For a 3.3V supply voltage with 37.5-MHz reference frequency, the PLL attains 1.2-GHz oscillation frequency, 10 ps dead-zone, and 1.5 us locked time. The frequency-double circuit is designed based on a bridge rectification type. A duplicate output frequency, 2.4-GHz, is generated. The average power consumption of the overall architecture is about 7.5mW.

Original languageEnglish
Pages1053-1056
Number of pages4
Publication statusPublished - 2004 Dec 1
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 2004 Dec 62004 Dec 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period04-12-0604-12-09

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Wu, M. F., Lin, Z. M., Chen, J. D., & Liu, K. H. (2004). A rapid acquisition phase-locked loop with frequency-double circuit operated in 2.4-GHZ band. 1053-1056. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.